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IEEE Micro

Issue 1 • Date Jan.-Feb. 2011

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Displaying Results 1 - 21 of 21
  • [Front cover]

    Publication Year: 2011, Page(s): c1
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  • [Front cover]

    Publication Year: 2011, Page(s): c2
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  • [Advertisement]

    Publication Year: 2011, Page(s): 1
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  • Contents

    Publication Year: 2011, Page(s): c2
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  • [Masthead]

    Publication Year: 2011, Page(s): 3
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  • A Solid Past, A Vital Future

    Publication Year: 2011, Page(s):4 - 5
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  • Top Picks [Guest editors' introduction]

    Publication Year: 2011, Page(s):6 - 10
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  • Virtualized ECC: Flexible Reliability in Main Memory

    Publication Year: 2011, Page(s):11 - 19
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (322 KB) | HTML iconHTML

    Virtualized error checking and correcting (ECC) is a scheme that virtualizes memory-error correction. Unlike traditional uniform ECC, which provides a fixed level of error tolerance, virtualized ECC enables flexible memory protection by mapping redundant information needed for correcting errors onto the memory namespace. Additionally, virtualized ECC enables error-correction mechanisms that can ad... View full abstract»

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  • Voltage Noise in Production Processors

    Publication Year: 2011, Page(s):20 - 28
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2227 KB) | HTML iconHTML

    Voltage variations are a major challenge in processor design. Here, researchers characterize the voltage noise characteristics of programs as they run to completion on a production Core 2 Duo processor. Furthermore, they characterize the implications of resilient architecture design for voltage variation in future systems. View full abstract»

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  • Aérgia: A Network-on-Chip Exploiting Packet Latency Slack

    Publication Year: 2011, Page(s):29 - 41
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (855 KB) | HTML iconHTML

    A traditional Network-on-Chip (NoC) employs simple arbitration strategies, such as round robin or oldest first, which treat packets equally regardless of the source applications' characteristics. This is suboptimal because packets can have different effects on system performance. We define slack as a key measure for characterizing a packet's relative importance. Aérgia introduces new route... View full abstract»

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  • Cohesion: An Adaptive Hybrid Memory Model for Accelerators

    Publication Year: 2011, Page(s):42 - 55
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (723 KB) | HTML iconHTML

    Cohesion is a hybrid memory model that enables fine-grained temporal data reassignment between hardware- and software-managed coherence domains, allowing systems to support both. Cohesion can dynamically adapt to the sharing needs of both applications and runtimes requiring neither copy operations nor multiple address spaces. View full abstract»

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  • Data Marshaling for Multicore Systems

    Publication Year: 2011, Page(s):56 - 64
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (847 KB) | HTML iconHTML

    Dividing a program into segments and executing each segment at the core best suited to run it can improve performance and save power. When consecutive segments run on different cores, accesses to intersegment data incur cache misses. Data Marshaling eliminates such cache misses by identifying and marshaling the necessary intersegment data when a segment is shipped to a remote core. View full abstract»

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  • ReMAP: A Reconfigurable Architecture for Chip Multiprocessors

    Publication Year: 2011, Page(s):65 - 77
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (898 KB) | HTML iconHTML

    ReMAP is a reconfigurable architecture for accelerating and parallelizing applications within a heterogeneous chip multiprocessor (CMP). Clusters of cores share a common reconfigurable fabric adaptable for individual thread computation or fine-grained communication with integrated computation. ReMAP demonstrates significantly higher performance and energy efficiency than hard-wired communication-o... View full abstract»

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  • Thread Cluster Memory Scheduling

    Publication Year: 2011, Page(s):78 - 89
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (514 KB) | HTML iconHTML

    Memory schedulers in multicore systems should carefully schedule memory requests from different threads to ensure high system performance and fair, fast progress of each thread. No existing memory scheduler provides both the highest system performance and highest fairness. Thread Cluster Memory scheduling is a new algorithm that achieves the best of both worlds by differentiating latency-sensitive... View full abstract»

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  • Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue

    Publication Year: 2011, Page(s):90 - 98
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (749 KB) | HTML iconHTML

    To alleviate bottlenecks in this era of many-core architectures, the authors propose a virtual write queue to expand the memory controller's scheduling window through visibility of cache behavior. Awareness of the physical main memory layout and a focus on writes can shorten both read and write average latency, reduce memory power consumption, and improve overall system performance. View full abstract»

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  • CHOP: Integrating DRAM Caches for CMP Server Platforms

    Publication Year: 2011, Page(s):99 - 108
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (415 KB) | HTML iconHTML

    Integrating large DRAM caches is a promising way to address the memory bandwidth wall issue in the many-core era. However, organizing and implementing a large DRAM cache imposes a trade-off between tag space overhead and memory bandwidth consumption. CHOP (Caching Hot Pages) addresses this trade-off through three filter-based DRAM-caching techniques. View full abstract»

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  • Address Translation Aware Memory Consistency

    Publication Year: 2011, Page(s):109 - 118
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (543 KB) | HTML iconHTML

    Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation systems. Detecting bugs and faults requires a clear specification of correct behavior. A new framework for address translation aware memory consistency models addresses this need. View full abstract»

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  • Security Refresh: Protecting Phase-Change Memory against Malicious Wear Out

    Publication Year: 2011, Page(s):119 - 127
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (697 KB) | HTML iconHTML

    As dynamic RAM scaling approaches its physical limit, phase-change memory is the most mature and well-studied option for potential DRAM replacement. However, malicious wear-out attacks can exploit PCM's limited write endurance. To address this, a low-cost wear-leveling scheme can dynamically randomize the data addresses across the entire address space and obfuscate their actual locations from user... View full abstract»

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  • Digital Dark Matter

    Publication Year: 2011, Page(s): 128
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (239 KB) | HTML iconHTML

    Economists need a label for some important building blocks of the digital economy that we do not measure using standard tools. Many indirect symptoms indicate their growth and importance. Many labels have been proposed-invisible infrastructure and private provision of public goods. Most digital dark matter does not show up in GDP because it is not part of a pecuniary transaction-namely, any trade ... View full abstract»

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  • [Advertisement - Back cover]

    Publication Year: 2011, Page(s): c3
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    Publication Year: 2011, Page(s): c4
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Aims & Scope

IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems.

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Meet Our Editors

Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center