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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 2 • Date Feb. 2011

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Displaying Results 1 - 22 of 22
  • Table of contents

    Publication Year: 2011 , Page(s): C1
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  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2011 , Page(s): C2
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  • Alias Rejection of Continuous-Time \Delta \Sigma Modulators With Switched-Capacitor Feedback DACs

    Publication Year: 2011 , Page(s): 233 - 243
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (971 KB) |  | HTML iconHTML  

    Continuous-time ΔΣ modulators (CTDSMs) with switched-capacitor (SC) feedback digital-to-analog converters (DACs) are relatively less sensitive to clock jitter when compared to converters that use non-return-to-zero feedback DACs. However, as we show in this paper, using an SC DAC can seriously compromise the alias rejection of the modulator, thereby nullifying one of the principal advantages of continuous-time operation. We give an intuitive understanding, as well as an analytical basis, for computing the signal transfer function of CTDSMs with SC DACs. We propose power-efficient circuit techniques to improve alias rejection in such modulators and give experimental results that illustrate some of our ideas. View full abstract»

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  • A Polar-Transmitter Architecture Using Multiphase Pulsewidth Modulation

    Publication Year: 2011 , Page(s): 244 - 252
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1269 KB) |  | HTML iconHTML  

    This paper presents a transmitter architecture based on a pulse-modulated polar transmitter using multiphase pulsewidth modulation. The modulation to the radio-frequency input signal, instead of conventional drain modulation, significantly reduces the circuit complexity, while the multiphase modulation technique reduces the out-of-band emissions. An 836.5-MHz four-phase prototype transmitter using four class-C power amplifiers in parallel was constructed. Using the transmitter, single-phase, two-phase, and four-phase pulsewidth modulated signals were tested to verify the benefits of using the proposed multiphase architecture. Using a CDMA2000 1X signal, 46.8% efficiency at a 29-dBm output power level was measured while passing the spectral-mask requirements without using any kind of digital predistortion or calibration. View full abstract»

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  • Clock-Jitter-Tolerant Wideband Receivers: An Optimized Multichannel Filter-Bank Approach

    Publication Year: 2011 , Page(s): 253 - 263
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1425 KB) |  | HTML iconHTML  

    Clock jitter is one of the most fundamental obstacles in realizing future generations of wideband receivers. Stringent jitter specifications in the sampling clocks of high-performance single-channel and multichannel time-interleaved analog-to-digital converters severely limit the evolution of baseband receivers. This paper presents an analytical framework for the design of clock-jitter-tolerant low-order multichannel filter-bank receivers, with techniques to dramatically lower the sampling-clock-jitter specifications. Although it is well understood that high-order frequency-channelized receivers provide higher tolerance to sampling jitter, this paper shows that low-order bandwidth-optimized multichannel receivers can achieve similar sampling-jitter tolerance. Additionally, this paper presents design tradeoffs and specifications of an example multichannel receiver that can process a 5-GHz baseband signal with 40 dB of signal-to-noise-ratio using sampling clocks that can tolerate up to 5 prmss clock jitter. In comparison, existing architectures based on time-interleaving require 0.5 prmss clock jitter for the given specifications. This extreme jitter tolerance allows for relaxed design of clocking systems, which averts a major roadblock in future wideband-communication-receiver development and provides the potential to enable several high-data-rate communication applications. View full abstract»

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  • A Discrete-Time Model for the Design of Type-II PLLs With Passive Sampled Loop Filters

    Publication Year: 2011 , Page(s): 264 - 275
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (888 KB) |  | HTML iconHTML  

    Type-II charge-pump (CP) phase-locked loop (PLLs) are used extensively in electronic systems for frequency synthesis. Recently, a passive sampled loop filter (SLF) has been shown to offer major benefits over the conventional continuous-time loop filter traditionally used in such PLLs. These benefits include greatly enhanced reference spur suppression, elimination of CP pulse-position modulation nonlinearity, and, in the case of phase noise cancelling fractional-N PLLs, improved phase noise cancellation. The main disadvantage of the SLF to date has been the lack of a linear time-invariant (LTI) model with which to perform the system-level design of SLF-based PLLs. Without such a model, designers are forced to rely on trial and error iteration supported by lengthy transient simulations. This paper presents an accurate LTI model of SLF-based type-II PLLs that eliminates this disadvantage. View full abstract»

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  • Noise and Nonlinearity Modeling of Active Mixers for Fast and Accurate Estimation

    Publication Year: 2011 , Page(s): 276 - 289
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1156 KB) |  | HTML iconHTML  

    This paper presents a model of active mixers for a fast and accurate estimation of noise and nonlinearity. Based on closed-form expressions, this model estimates the noise figure, IIP3, and IIP2 of the time-varying mixer by a limited number of time-invariant circuit calculations. The model shows that the decreasing transistor output resistance, together with the low supply voltage in deep-submicrometer technologies, significantly contributes to the flicker-noise leakage. Design insights for low flicker noise are then presented. The model also shows that the slope of the LO signal has a significant effect on IIP2, while it has a little effect on IIP3. A new IP2 calibration technique using slope tuning is presented. View full abstract»

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  • Low-Power Discrete Fourier Transform for OFDM: A Programmable Analog Approach

    Publication Year: 2011 , Page(s): 290 - 298
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1000 KB) |  | HTML iconHTML  

    The modulation and demodulation blocks in an orthogonal frequency-division multiplexing (OFDM) system are typically implemented digitally using a fast Fourier transform circuit. We propose an analog implementation of an OFDM demodulator as a means for reducing power consumption. The proposed receiver implements the discrete Fourier transform (DFT) as a vector-matrix multiplier using floating-gate transistors on a field-programmable analog array (FPAA). The DFT coefficients can be tuned to counteract an inherent device mismatch by adjusting the amount of electrical charge stored in the floating-gate transistors. When compared to a digital field-programmable gate array implementation, the analog FPAA implementation of the DFT reduces power consumption at the cost of a slight performance degradation. Considering the errors in the DFT coefficients as intersymbol interference, the performance degradation can be further mitigated by employing a least mean-square or minimum mean-square-error equalizer. View full abstract»

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  • A General Analytical Tool for the Design of Vibration Energy Harvesters (VEHs) Based on the Mechanical Impedance Concept

    Publication Year: 2011 , Page(s): 299 - 311
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (606 KB) |  | HTML iconHTML  

    This paper reports on a new approach for the analysis and design of vibration-to-electricity converters [vibration energy harvesters (VEHs)] operating in the mode of strong electromechanical coupling. The underlying concept is that the mechanical impedance is defined for a nonlinear electromechanical transducer on the basis of an equivalence between electrical and mechanical systems. This paper demonstrates how the mechanical impedance of the transducer depends not only on the geometry and the nature of the electromechanical transducer itself but also on the topology and on the operation mode of the conditioning circuit. The analysis is developed for resonant harvesters and is based on the first-harmonic method. It is applied to three electrostatic harvesters using an identical conditioning circuit but employing transducers with different geometries. For each of the three configurations, the mechanical impedance of the transducer is calculated and then used to determine the optimal electrical operation mode of the conditioning circuit, allowing a desired amplitude of the mobile-mass vibration to be obtained. This paper highlights how the parameters of the conditioning circuit and of the transducer impact the transducer's mechanical impedance, directly affecting the impedance matching between the energy source (resonator) and the transducer. This technique permits the design of highly efficient VEHs whatever the means of transduction. View full abstract»

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  • Theory of Injection-Locked Oscillator Phase Noise

    Publication Year: 2011 , Page(s): 312 - 325
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (506 KB) |  | HTML iconHTML  

    The paper describes the development of a model for the calculation of noise-driven phase response of an injection-locked oscillator perturbed by Gaussian white sources. Being based on the state space formalism the framework is unified encompassing all circuit topologies and methods of unilateral coupling. We thus avoid reverting to the kind of simplified block-diagram description that one finds in previously published works on the topic and our approach furthermore allows for all the main results and model parameters to be derived numerically based on the netlist description of the circuit. To our knowledge this constitutes the first attempt at an ILO phase-noise description not relying on block diagrams or other such phenomenological modelling strategies. View full abstract»

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  • Exponential Stability, Semistability, and Boundedness of a Multi-ANF System

    Publication Year: 2011 , Page(s): 326 - 335
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB) |  | HTML iconHTML  

    A nonlinear system being composed of multiadaptive notch filters in parallel is introduced to track the sinusoidal components of an almost periodic signal and estimate their frequencies and amplitudes. An almost periodic nonlinear dynamic system for estimation of frequencies is achieved after the existence of a slow integral manifold is proved and results in a nonlinear autonomous system with averaging method employed. Three types of local stability of the autonomous system, the exponential stability in isolated equilibrium point and the semistability on center manifold and the ultimate boundedness under unknown periodic disturbance, are respectively investigated. The transient performance is affected by frequency adaptive gain independent of bandwidth parameter. The validity of the proposed algorithm is verified by simulation results. View full abstract»

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  • A Graphical Approach to Prove Contraction of Nonlinear Circuits and Systems

    Publication Year: 2011 , Page(s): 336 - 348
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (819 KB) |  | HTML iconHTML  

    This paper derives a novel approach to prove contraction of nonlinear dynamical systems, based on the use of non-Euclidean norms and their associated matrix measures. A graphical procedure is developed to derive conditions for a system to be contracting. Such conditions can also be used to design control strategies to make a system contracting, or to design consensus and synchronization strategies for networks of nonlinear oscillators. After presenting the main steps of the approach and its proof, both for continuous-time and discrete-time systems, we illustrate the theoretical derivations on a set of representative examples. View full abstract»

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  • Robust H_{\infty } Synchronization Design of Nonlinear Coupled Network via Fuzzy Interpolation Method

    Publication Year: 2011 , Page(s): 349 - 362
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (618 KB) |  | HTML iconHTML  

    In this paper, the H theory is introduced to investigate the robustness and design of synchronization nonlinear coupled network. The H synchronization performance is defined as the disturbance attenuation ability for a synchronized coupled network. To measure the H synchronization performance of a nonlinear coupled network, we need to solve a Hamilton-Jacobi inequality (HJI), which is hard to treat directly. Hence, a Takagi-Sugeno fuzzy system is employed to approximate the nonlinear coupled network, so that the HJI can be replaced by a set of linear matrix inequalities. Furthermore, based on this H synchronization performance, a robust nonlinear coupled network with a prescribed H synchronization performance can be designed for a given network topology. In the robust H synchronization network, our design task is to specify the minimum coupling strengths of the corresponding links in the network topology such that the coupled network cannot only synchronize but also attenuate the external disturbance below a prescribed level. Since the design of robust H synchronization network leads to a set of bilinear matrix inequalities (BMIs), a two-step algorithm is proposed to solve the BMI-constrained optimization problem. The time-delay effect on the synchronization of coupled network is also discussed. View full abstract»

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  • Evaluation of Gunshot Detection Algorithms

    Publication Year: 2011 , Page(s): 363 - 373
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1293 KB) |  | HTML iconHTML  

    Six preprocessing algorithms for the detection of firearm gunshots are statistically evaluated, using the receiver operating characteristic method as a previous feasibility metric for their implementation on a low-power VLSI circuit. Circuits are intended to serve as the input detection sensors of a low-power environmental surveillance network. Some possible VLSI implementations for the evaluated algorithms are also evaluated. Results indicate that the use of wavelet bank filters, either discrete or continuous, might be the best choice in terms of the compromise between detection efficiency and the power requirements of the intended application. View full abstract»

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  • Solving Large-Scale Hybrid Circuit-Antenna Problems

    Publication Year: 2011 , Page(s): 374 - 387
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1301 KB) |  | HTML iconHTML  

    Motivated by different applications in circuits, electromagnetics, and optics, this paper is concerned with the synthesis of a particular type of linear circuit, where the circuit is associated with a control unit. The objective is to design a controller for this control unit such that certain specifications on the parameters of the circuit are satisfied. It is shown that designing a control unit in the form of a switching network is an NP-complete problem that can be formulated as a rank-minimization problem. It is then proven that the underlying design problem can be cast as a semidefinite optimization if a passive network is designed instead of a switching network. Since the implementation of a passive network may need too many components, the design of a decoupled (sparse) passive network is subsequently studied. This paper introduces a tradeoff between design simplicity and implementation complexity for an important class of linear circuits. The superiority of the developed techniques is demonstrated by different simulations. In particular, for the first time in the literature, a wavelength-size passive antenna is designed, which has an excellent beamforming capability and which can concurrently make a null in at least eight directions. View full abstract»

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  • Stabilization of a Class of Linear Systems With Input Delay and the Zero Distribution of Their Characteristic Equations

    Publication Year: 2011 , Page(s): 388 - 401
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (728 KB) |  | HTML iconHTML  

    This paper is concerned with stabilization of linear systems with arbitrarily large but bounded time-varying delay in the input. A pole assignment based low gain feedback design is adopted to solve the problem. Both delay-dependent and delay-independent results are presented and a series of sufficient conditions for guaranteeing the stability of the closed-loop system are established. By using properties of this class of low gain feedback laws and the properties of certain transcendental equations, distribution of the zeros of the closed-loop characteristic equation is described. As a result, a necessary and sufficient condition is identified that guarantees the stability of the closed-loop system. A numerical example is given to illustrate the effectiveness of the proposed approach. View full abstract»

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  • Efficient Partial-Parallel Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes

    Publication Year: 2011 , Page(s): 402 - 414
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB) |  | HTML iconHTML  

    Nonbinary low-density parity-check (NB-LDPC) codes constructed over GF(q) (q >; 2) can achieve higher coding gain than binary LDPC codes when the code length is moderate. A complete partial-parallel decoder architecture based on the Min-max algorithm is proposed for quasi-cyclic NB-LDPC codes in this paper. A novel scheme and corresponding architecture are developed to implement the elementary step of the check node processing. In our design, layered decoding is applied and only nm <; q messages are kept on each edge of the associated Tanner graph. The computation units and the scheduling of the computations are optimized in the context of layered decoding to reduce the area requirement and increase the speed. This paper also introduces an overlapped method for the check node processing among different layers to further speed up the decoding. From complexity and latency analysis, our design is much more efficient than any previous design. Our proposed decoder for a (744, 653) code over GF(25) has also been synthesized on a Xilinx Virtex-2 Pro FPGA device. It can achieve a throughput of 9.30 Mbps when 15 decoding iterations are carried out. View full abstract»

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  • Processing-Task Arrangement for a Low-Complexity Full-Mode WiMAX LDPC Codec

    Publication Year: 2011 , Page(s): 415 - 428
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1643 KB) |  | HTML iconHTML  

    In this paper, we propose dividing the decoding operations of a variety of irregular quasi-cyclic (QC) low-density parity-check (LDPC) codes into several smaller tasks. An algorithm is devised in order to arrange these tasks in a similar form such that a highly reusable multimode architecture can be designed to process these tasks. For this task-based decoder, the associated memory access can be accomplished with the help of the proposed address generators. Using this approach, the difficulty of designing a low-complexity multimode decoder, which is capable of supporting a variety of irregular QC-LDPC codes, can be overcome. Layered encoding that enables the routing networks and memory for decoding to be reused for the encoding is also proposed. Using these techniques, a multimode codec which can support all 114 WiMAX LDPC codes is designed and implemented in a 90-nm process. The full-mode WiMAX codec achieves a moderate encoding (decoding) throughput of 800 Mb/s (200 Mb/s) and occupies an area of only 0.679 mm2. View full abstract»

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  • On the Use of Soft-Decision Error-Correction Codes in nand Flash Memory

    Publication Year: 2011 , Page(s): 429 - 439
    Cited by:  Papers (37)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (641 KB) |  | HTML iconHTML  

    As technology continues to scale down, NAND Flash memory has been increasingly relying on error-correction codes (ECCs) to ensure the overall data storage integrity. Although advanced ECCs such as low-density parity-check (LDPC) codes can provide significantly stronger error-correction capability over BCH codes being used in current practice, their decoding requires soft-decision log-likelihood ratio (LLR) information. This results in two critical issues. First, accurate calculation of LLR demands fine-grained memory-cell sensing, which nevertheless tends to incur implementation overhead and access latency penalty. Hence, it is critical to minimize the fine-grained memory sensing precision. Second, accurate calculation of LLR also demands the availability of a memory-cell threshold-voltage distribution model. As the major source for memory-cell threshold-voltage distribution distortion, cell-to-cell interference must be carefully incorporated into the model. However, these two critical issues have not been ever addressed in the open literature. This paper attempts to address these open issues. We derive mathematical formulations to approximately model the threshold-voltage distribution of memory cells in the presence of cell-to-cell interference, based on which the calculation of LLRs is mathematically formulated. This paper also proposes a nonuniform memory sensing strategy to reduce the memory sensing precision and, thus, sensing latency while still maintaining good error-correction performance. In addition, we investigate these design issues under the scenario when we can also sense interfering cells and hence explicitly estimate cell-to-cell interference strength. We carry out extensive computer simulations to demonstrate the effectiveness and involved tradeoffs, assuming the use of LDPC codes in 2-bits/cell NAND Flash memory. View full abstract»

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  • Leading the field since 1884 [advertisement]

    Publication Year: 2011 , Page(s): 440
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    Freely Available from IEEE
  • IEEE Circuits and Systems Society Information

    Publication Year: 2011 , Page(s): C3
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers Information for authors

    Publication Year: 2011 , Page(s): C4
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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras