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Computers, IEEE Transactions on

Issue 3 • Date March 2011

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Displaying Results 1 - 16 of 16
  • [Front cover]

    Publication Year: 2011 , Page(s): c1
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  • [Inside front cover]

    Publication Year: 2011 , Page(s): c2
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  • A Management Strategy for the Reliability and Performance Improvement of MLC-Based Flash-Memory Storage Systems

    Publication Year: 2011 , Page(s): 305 - 320
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3164 KB) |  | HTML iconHTML  

    Cost has been a major driving force in the development of the flash-memory technology. Because of this, serious challenges are now faced for future products on reliability and performance requirements. In this work, we propose a management strategy to resolve the reliability and performance problems of many flash-memory products. A three-level address translation architecture with an adaptive block mapping mechanism is proposed to accelerate the address translation process with a limited amount of the RAM usage. Parallelism of operations over multiple chips is also explored with the considerations of the write constraints of advanced multilevel cell flash-memory chips. The capability of the proposed approach is analyzed with reliability considerations and evaluated by experiments over realistic workloads with respect to the reliability and performance improvement. View full abstract»

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  • High-Performance Scalable Flash File System Using Virtual Metadata Storage with Phase-Change RAM

    Publication Year: 2011 , Page(s): 321 - 334
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2873 KB) |  | HTML iconHTML  

    Several flash file systems have been developed based on the physical characteristics of NAND flash memory. However, previous flash file systems have performance overhead and scalability problems caused by metadata management in NAND flash memory. In this paper, we present a flash file system called PFFS2. PFFS2 stores all metadata into virtual metadata storage, which employs Phase-change RAM (PRAM). PRAM is a next-generation nonvolatile memory and will be good for dealing with word-level read/write of small-size data. Based on the virtual metadata storage, PFFS2 can manage metadata in a virtually fixed location and through byte-level in-place updates. Therefore, the performance of PFFS2 is 38 percent better than YAFFS2 for small file read/write while matching YAFFS2 performance for large file. Virtual metadata storage is particularly effective in decreasing the burden of computational and I/O overhead of garbage collection. In addition, PFFS2 maintains a 0.18 second mounting time and 284 KB memory usage in spite of increases in NAND flash memory size. We also propose a wear-leveling solution for PRAM in virtual metadata storage and greatly reduce the total write count of NAND flash memory. In addition, the life span of PFFS2 is longer than other flash file systems. View full abstract»

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  • Using Lossless Data Compression in Data Storage Systems: Not for Saving Space

    Publication Year: 2011 , Page(s): 335 - 345
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1428 KB) |  | HTML iconHTML  

    Lossless data compression for data storage has become less popular as mass data storage systems are becoming increasingly cheap. This leaves many files stored on mass data storage media uncompressed although they are losslessly compressible. This paper proposes to exploit the lossless compressibility of those files to improve the underlying storage system performance metrics such as energy efficiency and access speed, other than saving storage space as in conventional practice. The key idea is to apply runtime lossless data compression to enable an opportunistic use of a stronger error correction code (ECC) with more coding redundancy in data storage systems, and trade such opportunistic extra error correction capability to improve other system performance metrics in the runtime. Since data storage is typically realized in the unit of equal-sized sectors (e.g., 512 B or 4 KB user data per sector), we only apply this strategy to each individual sector independently in order to be completely transparent to the firmware, operating systems, and users. Using low-density parity check (LDPC) code as ECC in storage systems, this paper quantitatively studies the effectiveness of this design strategy in both hard disk drives and NAND flash memories. For hard disk drives, we use this design strategy to reduce average hard disk drive read channel signal processing energy consumption, and results show that up to 38 percent read channel energy saving can be achieved. For NAND flash memories, we use this design strategy to improve average NAND flash memory write speed, and results show that up to 36 percent write speed improvement can be achieved for 2 bits/cell NAND flash memories. View full abstract»

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  • Scalable Pattern Matching on Multicore Platform via Dynamic Differentiated Distributed Detection (D⁴)

    Publication Year: 2011 , Page(s): 346 - 359
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3753 KB) |  | HTML iconHTML  

    Pattern Matching (PM) is a key building block for many emerging network applications. Modern multicore platforms are becoming performance competitive with traditional hardware solutions, which are expensive and hard to adapt to the rapid diversification of Internet applications. However, due to uneven network flow sizes and the need to retain packet order within each flow, traditional parallel processing models using packet flows as the basic unit to partition the workload cannot fully take advantage of multicore platforms' power, exhibiting low CPU utilization and poor scalability with increasing numbers of CPUs or cores. In this paper, we propose a novel parallel inspection model called Dynamic Differentiated Distributed Detection (D4). D4 deploys balanced parallel detection by adding one more dimension on PM workload partition. The pattern set is prepartitioned into several subsets so as to distribute the workload of the hot flows across multiple cores while still maintaining packet order within each flow. We also show theoretically that higher number of subsets leads to higher algorithmic overhead. To achieve optimal throughput for all flow size distributions, D4 prepartitions the pattern set in several ways for use in different detection modes beforehand, and then, dynamically switches among these modes on-the-fly according to the flow and runtime information it senses. D4 also allows multiple PM algorithms to work simultaneously on different pattern subsets. According to several heuristics and the algorithms' characteristics, the detection mode selection and subset partitioning algorithms are designed to maximize the CPU/core utilization while avoiding unnecessary overheads. Experiments show that D4 features high core utilization and low overhead, thus achieving distinct performance gains against traditional load balancing schemes, as shown by experimental results using real-world pattern sets and traffi- - c traces. View full abstract»

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  • EAD and PEBD: Two Energy-Aware Duplication Scheduling Algorithms for Parallel Tasks on Homogeneous Clusters

    Publication Year: 2011 , Page(s): 360 - 374
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1702 KB) |  | HTML iconHTML  

    High-performance clusters have been widely deployed to solve challenging and rigorous scientific and engineering tasks. On one hand, high performance is certainly an important consideration in designing clusters to run parallel applications. On the other hand, the ever increasing energy cost requires us to effectively conserve energy in clusters. To achieve the goal of optimizing both performance and energy efficiency in clusters, in this paper, we propose two energy-efficient duplication-based scheduling algorithms-Energy-Aware Duplication (EAD) scheduling and Performance-Energy Balanced Duplication (PEBD) scheduling. Existing duplication-based scheduling algorithms replicate all possible tasks to shorten schedule length without reducing energy consumption caused by duplication. Our algorithms, in contrast, strive to balance schedule lengths and energy savings by judiciously replicating predecessors of a task if the duplication can aid in performance without degrading energy efficiency. To illustrate the effectiveness of EAD and PEBD, we compare them with a nonduplication algorithm, a traditional duplication-based algorithm, and the dynamic voltage scaling (DVS) algorithm. Extensive experimental results using both synthetic benchmarks and real-world applications demonstrate that our algorithms can effectively save energy with marginal performance degradation. View full abstract»

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  • A Parallel Efficient Architecture for Large Cryptographically Robust n × k (k>n/2) Mappings

    Publication Year: 2011 , Page(s): 375 - 385
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    We present a scalable, modular, memoryless, and reconfigurable parallel architecture to generate cryptographically robust mappings, which are useful in the construction of stream and block ciphers. It has been theoretically proved that the proposed architecture can be reconfigured to generate a large number of mappings, all of which have high nonlinearity, satisfies Strict Avalanche Criterion (SAC) and is robust against linear and differential cryptanalysis. The architecture can be also used to optimize the resiliency and algebraic degree. The architecture has been found to scale easily to handle large number of input variables, which is an important criterion in realizing nonlinear combiners for stream ciphers using Boolean functions. View full abstract»

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  • Complexity of Data Collection, Aggregation, and Selection for Wireless Sensor Networks

    Publication Year: 2011 , Page(s): 386 - 399
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (875 KB) |  | HTML iconHTML  

    Processing the gathered information efficiently is a key functionality for wireless sensor networks. In this paper, we study the time complexity, message complexity (number of messages used by all nodes), and energy cost complexity (total energy used by all nodes for transmitting messages) of some tasks, such as data collection (collecting raw data of all nodes to a sink), data aggregation (computing the aggregated value of data of all nodes), and queries for a multihop wireless sensor network of n nodes. We first present a lower bound on the complexity for the optimal methods, and then, for most of the tasks studied in this paper, we provide an (asymptotically matching) upper bound on the complexity by presenting efficient distributed algorithms to solve these problems. View full abstract»

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  • Efficient Data Gathering with Mobile Collectors and Space-Division Multiple Access Technique in Wireless Sensor Networks

    Publication Year: 2011 , Page(s): 400 - 417
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6220 KB) |  | HTML iconHTML  

    Recent years have witnessed a surge of interest in efficient data gathering schemes in wireless sensor networks (WSNs). In this paper, we address this issue by adopting mobility and space-division multiple access (SDMA) technique. Specifically, mobile collectors, called SenCars in this paper, work like mobile base stations and collect data from associated sensors via single-hop transmissions so as to achieve uniform energy consumption. We also apply SDMA technique to data gathering by equipping each SenCar with multiple antennas such that distinct compatible sensors may successfully make concurrent data uploading to a SenCar. To investigate the utility of the joint design of controlled mobility and SDMA technique, we consider two cases, where a single SenCar and multiple SenCars are deployed in a WSN, respectively. For the single SenCar case, we aim to minimize the total data gathering time, which consists of the moving time of the SenCar and the data uploading time of sensors, by exploring the trade-off between the shortest moving tour and the full utilization of SDMA. We refer to this problem as mobile data gathering with SDMA, or MDG-SDMA for short. We formalize it into an integer linear program (ILP) and propose three heuristic algorithms for it. In the multi-SenCar case, the sensing field is divided into several regions, each having a SenCar. We focus on minimizing the maximum data gathering time among different regions and refer to it as mobile data gathering with multiple SenCars and SDMA (MDG-MS) problem. Accordingly, we propose a region-division and tour-planning (RDTP) algorithm in which data gathering time is balanced among different regions. We carry out extensive simulations and the results demonstrate that our proposed algorithms significantly outperform single SenCar and non-SDMA schemes. View full abstract»

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  • Elementary Functions Hardware Implementation Using Constrained Piecewise-Polynomial Approximations

    Publication Year: 2011 , Page(s): 418 - 432
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4673 KB) |  | HTML iconHTML  

    A novel technique for designing piecewise-polynomial interpolators for hardware implementation of elementary functions is investigated in this paper. In the proposed approach, the interval where the function is approximated is subdivided in equal length segments and two adjacent segments are grouped in a segment pair. Suitable constraints are then imposed between the coefficients of the two interpolating polynomials in each segment pair. This allows reducing the total number of stored coefficients. It is found that the increase in the approximation error due to constraints between polynomial coefficients can easily be overcome by increasing the fractional bits of the coefficients. Overall, compared with standard unconstrained piecewise-polynomial approximation having the same accuracy, the proposed method results in a considerable advantage in terms of the size of the lookup table needed to store polynomial coefficients. The calculus of the coefficients of constrained polynomials and the optimization of coefficients bit width is also investigated in this paper. Results for several elementary functions and target precision ranging from 12 to 42 bits are presented. The paper also presents VLSI implementation results, targeting a 90 nm CMOS technology, and using both direct and Horner architectures for constrained degree-1, degree-2, and degree-3 approximations. View full abstract»

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  • Recoverable Robust Timetables: An Algorithmic Approach on Trees

    Publication Year: 2011 , Page(s): 433 - 446
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2719 KB) |  | HTML iconHTML  

    In the context of scheduling and timetabling, we study a challenging combinatorial problem which is very interesting for both practical and theoretical points of view. The motivation behind it is to cope with scheduled activities which might be subject to unavoidable disruptions, such as delays, occurring during the operational phase. The idea is to preventively plan some extra time for the scheduled activities in order to be "prepared” if a delay occurs, and absorb it without the necessity of rescheduling all the activities from scratch. This realizes the concept of designing robust timetables. During the planning phase, one should also consider recovery features that might be applied at runtime if disruptions occur. This leads to the concept of recoverable robust timetables. In this new concept, it is assumed that recovery capabilities are given as input along with the possible disruptions that must be considered. The main objective is the minimization of the overall needed time. The quality of a robust timetable is measured by the price of robustness, i.e., the ratio between the cost of the robust timetable and that of a nonrobust optimal timetable. We show that finding an optimal solution for this problem is NP-hard even though the topology of the network, which models dependencies among activities, is restricted to trees. However, we manage to design a paeudopolynomial time algorithm based on dynamic programming and apply it on both random networks and real case scenarios provided by Italian railways. We evaluate the effect of robustness on the scheduling of the activities and provide the price of robustness with respect to different scenarios. We experimentally show the practical effectiveness and efficiency of the proposed algorithm. View full abstract»

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  • IEEE and IEEE Computer Society Special Student Offer

    Publication Year: 2011 , Page(s): 447
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  • Distinguish yourself with the CSDP [advertisement]

    Publication Year: 2011 , Page(s): 448
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  • TC Information for authors

    Publication Year: 2011 , Page(s): c3
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  • [Back cover]

    Publication Year: 2011 , Page(s): c4
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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org