# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 48

Publication Year: 2011, Page(s):C1 - 278
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2011, Page(s): C2
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• ### Characterization and Design of Through-Silicon Via Arrays in Three-Dimensional ICs Based on Thermomechanical Modeling

Publication Year: 2011, Page(s):279 - 287
Cited by:  Papers (15)
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A general approach has been proposed for predicting the temperature and thermal stress fields of through-silicon-via (TSV) arrays in 3-D integrated circuits (ICs) based on a coupled-field finite-element (FE) method. The heat source under consideration is the active device layers of the ICs that are operating under load. Individual and combined effects of TSV array parameters, including TSV height,... View full abstract»

• ### A Charge Trap Folded nand Flash Memory Device With Band-Gap-Engineered Storage Node

Publication Year: 2011, Page(s):288 - 295
Cited by:  Papers (7)
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A charge trap folded NAND (FNAND) Flash memory device with band-gap-engineered (BE) storage node is proposed. Because of the compact cell layout without junction contacts, a NAND Flash memory is the most suitable memory medium for electronic appliances. Two memory cells are put together to have a common vertical channel, which enables one to achieve a theoretical near-30-nm technology. The resulti... View full abstract»

• ### Asymmetric Drain Spacer Extension (ADSE) FinFETs for Low-Power and Robust SRAMs

Publication Year: 2011, Page(s):296 - 308
Cited by:  Papers (59)  |  Patents (2)
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In this paper, we analyze and optimize FinFETs with asymmetric drain spacer extension (ADSE) that introduces a gate underlap only on the drain side. We present a physics-based discussion of current-voltage relationships, short channel effects, and leakage and show the application of ADSE FinFETs in 6T static random access memory (SRAM) bit cell. By exploiting asymmetry in current, we show that it ... View full abstract»

• ### An Insight Into the ESD Behavior of the Nanometer-Scale Drain-Extended NMOS Device—Part I: Turn-On Behavior of the Parasitic Bipolar

Publication Year: 2011, Page(s):309 - 317
Cited by:  Papers (6)
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A second-breakdown phenomenon (It2) in a drain-extended n-type metal-oxide-semiconductor (DENMOS) is associated with complex triggering of a parasitic bipolar transistor. Full comprehension of the problem requires 3-D modeling; however, there is even deficiency in the understanding of the phenomenon occurring in the 2-D cross-sectional plane. We present experiments and models to understand the phy... View full abstract»

• ### An Insight Into ESD Behavior of Nanometer-Scale Drain Extended NMOS (DeNMOS) Devices: Part II (Two-Dimensional Study-Biasing & Comparison With NMOS)

Publication Year: 2011, Page(s):318 - 326
Cited by:  Papers (3)
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In this paper, we present an analysis of drain extended n-channel metal-oxide-semiconductor (DeNMOS) and study the impact of both substrate and gate biasing on the regenerative avalanche injection phenomenon at the edge of drain contact. We will demonstrate that the flow and distribution of avalanche-generated holes and electrons are significantly impacted by biasing the gate and pumping current t... View full abstract»

• ### Monte Carlo Simulation of Leakage Currents in $hbox{TiN/ZrO}_{2}/hbox{TiN}$ Capacitors

Publication Year: 2011, Page(s):327 - 334
Cited by:  Papers (19)
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Leakage currents in TiN/high-κ-ZrO2/TiN capacitors were simulated by using a novel kinetic Monte Carlo algorithm specially designed to describe tunneling transport of charge carriers in high-κ dielectrics, including defect-assisted transport mechanisms. Comparing simulation results with experimental data, a model for electronic transport was established and validated. Tran... View full abstract»

• ### Transistor Mismatch Properties in Deep-Submicrometer CMOS Technologies

Publication Year: 2011, Page(s):335 - 342
Cited by:  Papers (30)
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Transistor mismatch data and analysis from poly/SiON and high-k/metal-gate (HKMG) bulk CMOS technologies are presented. It is found that the traditional mismatch figure of merit from the Pelgrom plot (AVT) continuously scales down as technology advances. Furthermore, the AVT values for both nFET and pFET in the HKMG technology are significantly reduced from poly/SiON technolo... View full abstract»

• ### DC Characterization of Tunnel Diodes Under Stable Non-Oscillatory Circuit Conditions

Publication Year: 2011, Page(s):343 - 347
Cited by:  Papers (9)
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A common problem in designing with Esaki tunneling diodes in circuits is parasitic oscillations, which occur when these devices are biased in their negative differential resistance (NDR) region. Because of this, the measured current-voltage (I-V) characteristics in the NDR region are usually incorrect, with sudden changes in current with voltage and a plateaulike waveform in this region. Using a f... View full abstract»

• ### A Novel Low-Bias Charge Concept for HBT/BJT Models Including Heterobandgap and Temperature Effects—Part I: Theory

Publication Year: 2011, Page(s):348 - 356
Cited by:  Papers (3)
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A new compact model approach is suggested for the low-bias base charge of homo- and heterojunction bipolar transistors. It is shown that the junction-related (Early) components of this charge depend on an effective doping density. This concept leads to an accurate description with the conventional capacitance-charge model formulas but using different parameters directly extracted from direct-curre... View full abstract»

• ### A Novel Low-Bias Charge Concept for HBT/BJT Models Including Heterobandgap and Temperature Effects—Part II: Implementation, Parameter Extraction and Verification

Publication Year: 2011, Page(s):357 - 363
Cited by:  Papers (3)
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A new compact model approach was suggested in Part I for the low-bias base charge of homo- and heterojunction bipolar transistors. Conventional capacitance-charge formulas with dc extracted parameters were shown to provide accurate description for the Moll-Ross-Gummel charge components. New parameters were introduced to account for BGN effects and Ge doping on the temperature behavior of SiGe tran... View full abstract»

• ### Effect of Channel Dopant Profile on Difference in Threshold Voltage Variability Between NFETs and PFETs

Publication Year: 2011, Page(s):364 - 369
Cited by:  Papers (29)
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The mechanism behind the threshold voltage VT variability difference between n- and p-type field-effect transistors (NFETs and PFETs, respectively) is investigated from the viewpoint of the channel dopant profile. First, the effect of the depth profile is investigated by comparing the VT variability among FETs with various depth channel profiles. It is clarified that the V View full abstract»

• ### Impact of HfTaO Buffer Layer on Data Retention Characteristics of Ferroelectric-Gate FET for Nonvolatile Memory Applications

Publication Year: 2011, Page(s):370 - 375
Cited by:  Papers (18)
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A p-channel metal-ferroelectric-insulator-silicon field-effect transistor (FET) with a 300-nm-thick SrBi2Ta2O9 (SBT) ferroelectric film and a 10-nm-thick HfTaO layer on silicon substrate was fabricated and characterized. The device shows a nearly unchanged memory window of about 0.9 V after a 2 × 1011-cycles fatigue test, an on/off current ratio o... View full abstract»

• ### Single-Electron Charging and Discharging Analyses in Ge-Nanocrystal Memories

Publication Year: 2011, Page(s):376 - 383
Cited by:  Papers (6)
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The transient charging/discharging of electrons in Ge-nanocrystal (NC) memories are measured by a pump-and-probe method that allows keeping track of the number of electrons per NC. The experiments are simulated with a quantum kinetic mechanical model based on the density-functional theory, which can describe the NCs' charging state. In the transient charging, electrons are captured faster than pre... View full abstract»

• ### On the High-Field Transport and Uniaxial Stress Effect in Ge PFETs

Publication Year: 2011, Page(s):384 - 391
Cited by:  Papers (11)
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Ge is one of the promising candidates for high-mobility channel material in future complementary metal-oxide-semiconductor technology. High-field transport in short-channel Ge p-channel field-effect transistors (PFETs) needs to be examined since device performance is determined by high-field velocity in quasi-ballistic transport regime. In this paper, ballisticity and the relationship between carr... View full abstract»

• ### A Physics-Based Three-Dimensional Analytical Model for RDF-Induced Threshold Voltage Variations

Publication Year: 2011, Page(s):392 - 403
Cited by:  Papers (12)
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In this paper, a 3-D analytical model is proposed to capture the threshold voltage, surface potential, and electric field variations induced by random dopant fluctuations in the channel region of metal-oxide-semiconductor field-effect transistors. The 3-D model treats the effect of each dopant separately and is based on fundamental laws of physics. The proposed approach enables determination of tr... View full abstract»

• ### Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor

Publication Year: 2011, Page(s):404 - 410
Cited by:  Papers (125)  |  Patents (2)
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In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the threshold voltage and also improve the average subthreshold slope, the nature of the output characteristics, and immunity against the drain-induced barrier lowering effects. We demonstrate that, if appropriate work fu... View full abstract»

• ### Measuring Holding Voltage Related to Homogeneous Current Flow in Wide ESD Protection Structures Using Multilevel TLP

Publication Year: 2011, Page(s):411 - 418
Cited by:  Papers (9)
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Due to the negative-differential-resistance-related instability, the current-density distribution in sufficiently wide devices exhibiting S-shaped I-V characteristics becomes inherently inhomogeneous along the device width. High-current-density on-state (i.e., a current filament) and low-current-density off-state regions are spontaneously formed, leading to the formation of a vertica... View full abstract»

• ### Work-Function-Tuned TiN Metal Gate FDSOI Transistors for Subthreshold Operation

Publication Year: 2011, Page(s):419 - 426
Cited by:  Papers (18)  |  Patents (1)
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The effective work function of a reactively sputtered TiN metal gate is shown to be tunable from 4.30 to 4.65 eV. The effective work function decreases with nitrogen flow during reactive sputter deposition. Nitrogen annealing increases the effective work function and reduces Dit. Thinner TiN improves the variation in effective work function and reduces gate dielectric charge. Dop... View full abstract»

• ### Analysis of Transconductance $(g_{m})$ in Schottky-Barrier MOSFETs

Publication Year: 2011, Page(s):427 - 432
Cited by:  Papers (22)
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This paper experimentally investigates the unique behavior of transconductance (gm) in the Schottky-barrier metal-oxide-semiconductor field-effect transistors (SB-MOSFETs) with various silicide materials. When the Schottky-barrier height (SBH) or a scaling parameter is not properly optimized, a peculiar shape of gm is observed. Thus, gm can be used as a novel metric that exhib... View full abstract»

• ### Effect of Localized Interface Charge on the Threshold Voltage of Short-Channel Undoped Symmetrical Double-Gate MOSFETs

Publication Year: 2011, Page(s):433 - 440
Cited by:  Papers (21)
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An analytical threshold-voltage model of short-channel undoped symmetrical double-gate metal-oxide-semiconductor field-effect transistors including positive or negative interface charges near the drain is presented. The threshold-voltage model is derived based on an analytical solution for the potential distribution along the channel in the subthreshold region. Both potential and threshold-voltage... View full abstract»

• ### Evaluating the Aluminum-Alloyed $hbox{p}^{+}$ -Layer of Silicon Solar Cells by Emitter Saturation Current Density and Optical Microspectroscopy Measurements

Publication Year: 2011, Page(s):441 - 447
Cited by:  Papers (23)
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Surface-passivated and surface-unpassivated aluminum-alloyed p+-layers are characterized. By varying the firing conditions and the thickness of the screen-printed aluminum paste, different sheet resistances Rsh of the p+-layer were fabricated. The emitter saturation current density J0e plotted versus Rsh follows distinctly differ... View full abstract»

• ### A Surface-Potential-Based Compact Model for AlGaN/GaN MODFETs

Publication Year: 2011, Page(s):448 - 454
Cited by:  Papers (35)
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In this paper, a surface-potential-based (SP-based) model for AlGaN/GaN modulation-doped field-effect transistors (MODFETs) is built for the first time. First, a closed-form analytical approximation for the Fermi potential EF relative to the bottom of the conduction band at the AlGaN/GaN interface is presented and verified to be accurate enough under different biases and temperatures. Then,... View full abstract»

• ### Two-Dimensional Analytical Model for Concentration Profiles of Aluminum Implanted Into 4H-SiC (0001)

Publication Year: 2011, Page(s):455 - 459
Cited by:  Papers (2)
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A 2-D model of aluminum-ion implantation into 4H-SiC (0001) was developed and assessed through reverse current IR-voltage VR characteristics of p-n diodes. The model was based on a Monte Carlo simulation using a binary-collision approximation. For a moderate dose (1011 - 1013 cm-2), simulated isoconcentration contours were independent of the o... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy