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IEE Proceedings G - Circuits, Devices and Systems

Issue 6 • Dec. 1990

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Displaying Results 1 - 14 of 14
  • Testing of interconnection circuits in wafer-scale arrays

    Publication Year: 1990, Page(s):482 - 488
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (677 KB)

    An efficient testing algorithm for interconnection circuits, including programmable switches and data links in wafer-scale reconfigurable arrays is presented. Faulty programmable switches or data links are eliminated by finding fault-free paths in the switch grid obtained by isolating all computing units from the rest of a reconfigurable array. No internal test points are assumed. The algorithm is... View full abstract»

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  • Current-controlled linear MOS earthed and floating resistors and their application

    Publication Year: 1990, Page(s):479 - 481
    Cited by:  Papers (26)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (233 KB)

    A current-controlled linear MOS earthed resistor that requires only three transistors is realised by means of a new linearisation technique. A nonlinearity within +or-1.5% full scale in the 0-4 V voltage range for a 5 V supply is experimentally achieved with discrete MOS devices. However, much higher linearity can be expected if the ratio of two transistor sizes are chosen exactly, according to th... View full abstract»

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  • Oxide breakdown in a metal-SiO/sub 2/-Si capacitor: influence of the metal electrode

    Publication Year: 1990, Page(s):475 - 478
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (243 KB)

    The influence of the metal electrode, size, type and thickness on the breakdown field strength of a metal-SiO/sub 2/-Si capacitor with an insulating layer less than 100 AA thick is investigated. The results are interpreted in terms of stress at the SiO/sub 2/-Si interface.<> View full abstract»

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  • Simple high-frequency CMOS transconductor

    Publication Year: 1990, Page(s):470 - 474
    Cited by:  Papers (4)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (317 KB)

    A new transconductor, using only two transistors, is presented. It is based on standard inverter configurations and does not need matching of nMOS and pMOS transistors or of the power supply voltages. Reduction in nonlinearity is achieved by maintaining a zero offset condition. The circuit is not affected by variations in body effect as sources and substrates are connected to fixed voltages. Altho... View full abstract»

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  • Analysis of focused surface wave transducers

    Publication Year: 1990, Page(s):467 - 469
    Cited by:  Papers (2)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (183 KB)

    A new acoustic field analysis, based on the Huygens principles, is given for an elastic surface acoustic wave convolver made by using a focused transducer on a YZ-LiNbO/sub 3/ piezoelectric crystal. In the acoustic field analysis, a new slowness function approximation is suggested for the anisotropy of the medium, instead of the conventional parabolic slowness function. The acoustic field analysis... View full abstract»

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  • Modelling of the sidegating and the backgating effects in GaAs MESFETs

    Publication Year: 1990, Page(s):459 - 462
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (347 KB)

    Sidegating and backgating effects affect the I/V characteristics of a GaAs MESFET built on SI substrates. The basic charge trapping, process can be related to current flowing through the channel substrate interface. This effectively changes the channel thickness. For the side-gating effect, the observed voltage threshold for current pinch-off is explained by the breakdown of a parasitic lateral np... View full abstract»

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  • Safe sequencing of concurrent events in behavioural simulation

    Publication Year: 1990, Page(s):451 - 458
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (711 KB)

    A functional/behavioural simulator is described, in which the system to be simulated is modelled by defining its hierarchy and by specifying the descriptive function of the behaviour of its components. The functional model, based on the definition of strict and nonstrict functions, makes it possible to introduce and formally justify a simulation mechanism for safe sequencing of concurrent events i... View full abstract»

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  • Real number arithmetic for mixed behavioural and structural descriptions

    Publication Year: 1990, Page(s):446 - 450
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (356 KB)

    The authors describe extensions to the ELLA system for specifying hardware circuits containing mixed behavioural and structural real arithmetic, from the highest abstract level down to bit level. A consequence of these extensions is the provision of an extensive set of logical and arithmetic operators on arbitrary length arrays of bits in both signed and unsigned format. The authors outlines the r... View full abstract»

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  • Active and digital ladder-based allpass filters

    Publication Year: 1990, Page(s):439 - 445
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (447 KB)

    Ladder-based allpass filters are extended for active RLC, active RC, SC and digital realisations. The resulting circuits have the attractive properties of parallel structure and very low amplitude sensitivity to component changes. The analogue implementations are canonical with respect to the number of op amps and the digital ones are multiplier canonic. Detailed examples are given for SC designs ... View full abstract»

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  • Design of 2-D recursive filters with asymmetric half-plane lattice modelling

    Publication Year: 1990, Page(s):427 - 438
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (669 KB)

    A method, based on 2-D asymmetric half-plane lattice parameters, for the design of two dimensional (2-D) recursive digital filters is presented. The design procedure calculates the lattice parameter factors from the prescribed frequency characteristics. The order of the design is controlled by an a priori error criterion, corresponding to the minimum mean squared error between two successive stage... View full abstract»

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  • Chebyshev phase networks for pulse compressing and stretching

    Publication Year: 1990, Page(s):424 - 426
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (211 KB)

    A method for the direct synthesis of filters for pulse compressing and stretching, the phase of which approximates a Chebyshev squared phase in an arbitrary frequency region, is described. The procedure is based on the solution of a linear equation system that provides a final solution within a very small number of iterative cycles.<> View full abstract»

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  • Efficient systolic high speed architectures for delayed multipath two-dimensional FIR and IIR digital filtering

    Publication Year: 1990, Page(s):413 - 423
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (651 KB)

    Two novel efficient block-level systolic architectures for the high speed realisation of delayed multipath two-dimensional FIR and IIR digital filters are presented. With the new transformation method presented, an extra loop delay is allowed in the recursive part of the multipath structure of an IIR digital filter. Two methods for the stabilisation of the transformation method are also introduced... View full abstract»

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  • Switch-level timing verification for CMOS circuits: a semianalytic approach

    Publication Year: 1990, Page(s):405 - 412
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (548 KB)

    The authors describe a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model... View full abstract»

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  • Effects of cathode lengths and epitaxial layer widths on n 1+n1-δ(p +)n2-n2 +p+ and n1δ(p+)n2 p+ switching devices

    Publication Year: 1990, Page(s):463 - 466
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (188 KB)

    The author describes the effects of the n1-cathode length and the n2-epitaxial layer width on the I/V characteristics of two-state homojunction n 11-(p+-plane)-π 2-n2-p+ and n1-(p+-plane)-... View full abstract»

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