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IEEE Micro

Issue 6 • Date Nov.-Dec. 2010

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Displaying Results 1 - 17 of 17
  • [Front cover]

    Publication Year: 2010, Page(s): c1
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  • [Front cover]

    Publication Year: 2010, Page(s): c2
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  • Call for Papers

    Publication Year: 2010, Page(s): 1
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  • Contents

    Publication Year: 2010, Page(s): c2
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  • Masthead

    Publication Year: 2010, Page(s): 3
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  • Moving Forward

    Publication Year: 2010, Page(s):4 - 5
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  • Building Broadband Ahead of Digital Demand

    Publication Year: 2010, Page(s):6 - 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (461 KB) | HTML iconHTML

    Many governments today, especially outside the US, are considering making large subsidies for broadband. Some governments, such as South Korea's, have already done so, making next-generation broadband widely available. In the US, debates about subsidizing broadband touch two sets of overlapping issues. One set considers the benefits and costs of an expensive action: building wire-line broadband in... View full abstract»

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  • Rethinking Digital Design: Why Design Must Change

    Publication Year: 2010, Page(s):9 - 24
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1201 KB) | HTML iconHTML

    Because of technology scaling, power dissipation is today's major performance limiter. Moreover, the traditional way to achieve power efficiency, application-specific designs, is prohibitively expensive. These power and cost issues necessitate rethinking digital design. To reduce design costs, we need to stop building chip instances, and start making chip generators instead. Domain-specific chip g... View full abstract»

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  • Performance and Energy Implications of Many-Core Caches for Throughput Computing

    Publication Year: 2010, Page(s):25 - 35
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (509 KB) | HTML iconHTML

    Processors that target throughput computing often have many cores, which stresses the cache hierarchy. logically centralized, shared data storage is needed for many-core chips to provide high cache throughput for heavily read-write shared lines. techniques to reduce on-die and off-die traffic have a dramatic energy benefit for many-core chips. View full abstract»

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  • Putting Faulty Cores to Work

    Publication Year: 2010, Page(s):36 - 45
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB) | HTML iconHTML

    Necromancer, a robust and heterogeneous core coupling execution scheme, exploits a functionally dead core to improve system throughput by supplying hints regarding high-level program behavior. Necromancer partitions a chip multiprocessor system's cores into multiple groups, each of which shares a lightweight core that can be substantially accelerated using execution hints from the faulty core. View full abstract»

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  • Fast, Accurate, and Validated Full-System Software Simulation of x86 Hardware

    Publication Year: 2010, Page(s):46 - 56
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (637 KB) | HTML iconHTML

    This article presents a fast and accurate interval-based CPU timing model that is easily implemented and integrated in the COTSon full-system simulation infrastructure. Validation against real x86 hardware demonstrates the timing model's accuracy. The end result is a software simulator that faithfully simulates x86 hardware at a speed in the tens of MIPS range. View full abstract»

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  • Workload Reduction and Generation Techniques

    Publication Year: 2010, Page(s):57 - 65
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (727 KB) | HTML iconHTML

    Benchmarking is a fundamental aspect of computer system design. Recently proposed workload reduction and generation techniques include input reduction, sampling, code mutation, and benchmark synthesis. The authors discuss and compare these techniques along several criteria: whether they yield representative and short-running benchmarks, whether they can be used for both architecture and compiler e... View full abstract»

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  • Energy-Efficient Fast Fourier Transforms for Cognitive Radio Systems

    Publication Year: 2010, Page(s):66 - 76
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (904 KB) | HTML iconHTML

    An energy-efficient fast Fourier transform (FFT) algorithm for cognitive radio communication systems uses a homogeneous multiprocessor system on chip. The algorithm allows for pruning of inputs such that algorithm complexity can be reduced whenever several of the FFT inputs are zero. Results show that the pruning algorithm significantly reduces energy consumption compared to a nonpruned version. View full abstract»

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  • [Advertisement]

    Publication Year: 2010, Page(s): 77
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  • Being Geek

    Publication Year: 2010, Page(s): 78
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  • [Advertisement - Back cover]

    Publication Year: 2010, Page(s): c3
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  • [Advertisement - Back cover]

    Publication Year: 2010, Page(s): c4
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Aims & Scope

IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems.

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Meet Our Editors

Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center