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Solid-State Circuits, IEEE Journal of

Issue 1 • Date Jan. 2011

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Displaying Results 1 - 25 of 35
  • [Front cover]

    Publication Year: 2011 , Page(s): C1 - C4
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  • IEEE Journal of Solid-State Circuits publication information

    Publication Year: 2011 , Page(s): C2
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  • Table of contents

    Publication Year: 2011 , Page(s): 1 - 2
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  • Introduction to the Special Issue on the 2010 IEEE International Solid-State Circuits Conference

    Publication Year: 2011 , Page(s): 3 - 7
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  • Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE

    Publication Year: 2011 , Page(s): 8 - 17
    Cited by:  Papers (37)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1435 KB) |  | HTML iconHTML  

    Turbo-decoding for the 3GPP-LTE (Long Term Evolution) wireless communication standard is among the most challenging tasks in terms of computational complexity and power consumption of corresponding cellular devices. This paper addresses design and implementation aspects of parallel turbo-decoders that reach the 326.4 Mb/s LTE peak data-rate using multiple soft-input soft-output decoders that operate in parallel. To highlight the effectiveness of our design-approach, we realized a 3.57 mm2 radix-4based 8× parallel turbo-decoder ASIC in 0.13 μm CMOS technology achieving 390 Mb/s. At the more realistic 100 Mb/s LTE milestone targeted by industry today, the turbo-decoder consumes only 69 mW. View full abstract»

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  • A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation

    Publication Year: 2011 , Page(s): 18 - 31
    Cited by:  Papers (34)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2139 KB) |  | HTML iconHTML  

    Razor is a hybrid technique for dynamic detection and correction of timing errors. A combination of error detecting circuits and micro-architectural recovery mechanisms creates a system that is robust in the face of timing errors, and can be tuned to an efficient operating point by dynamically eliminating unused timing margins. Savings from margin reclamation can be realized as per device power-efficiency improvement, or parametric yield improvement for a batch of devices. In this paper, we apply Razor to a 32 bit ARM processor with a micro-architecture design that has balanced pipeline stages with critical memory access and clock-gating enable paths. The design is fabricated on a UMC 65 nm process, using industry standard EDA tools, with a worst-case STA signoff of 724 MHz. Based on measurements on 87 samples from split-lots, we obtain 52% power reduction for the overall distribution at 1 GHz operation. We present error rate driven dynamic voltage and frequency scaling schemes where runtime adaptation to PVT variations and tolerance of fast transients is demonstrated. All Razor cells are augmented with a sticky error history bit, allowing precise diagnosis of timing errors over the execution of test vectors. We show potential for parametric yield improvement through energy-efficient operation using Razor. View full abstract»

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  • A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM

    Publication Year: 2011 , Page(s): 32 - 41
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2572 KB) |  | HTML iconHTML  

    In this paper we introduce a 14-core application processor for multimedia mobile applications, implemented in 40 nm, with a 222 mW H.264 full high-definition (full-HD) video engine, a 124 mW 40 M-polygons/s 3D/2D graphics engine, and a video/audio multiprocessor for various Codecs and image processing. The application processor has 25 power domains to achieve coarse-grain power gating for adjusting to the required performance of wide range of multimedia applications. The simple on-chip power switch circuits perform less than 1 μs switching while reducing rush current. Furthermore, the Stacked Chip SoC (SCS) technology enables rewiring to the DRAM chip during assembly/packaging phase using a wire with 10 μm minimum pitch on Re-Distribution Layer (RDL) using electroplating. The peak memory bandwidth is 10.6 GB/s with an x512b SCS-DRAM interface, and the power consumption of this interface is 3.9 mW at 2.4 GB/s workload. View full abstract»

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  • A 345 mW Heterogeneous Many-Core Processor With an Intelligent Inference Engine for Robust Object Recognition

    Publication Year: 2011 , Page(s): 42 - 51
    Cited by:  Papers (30)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2584 KB) |  | HTML iconHTML  

    A heterogeneous many-core object recognition processor is proposed to realize robust and efficient object recognition on real-time video of cluttered scenes. Unlike previous approaches that simply aimed for high GOPS/W, we aim to achieve high Effective GOPS/W, or EGOPS/W, which only counts operations carried out on meaningful regions of an input image. This is achieved by the Unified Visual Attention Model (UVAM) which confines complex Scale Invariant Feature Transform (SIFT) feature extraction to meaningful object regions while rejecting meaningless background regions. The Intelligent Inference Engine (HE), a mixed-mode neuro-fuzzy inference system, performs the top-down familiarity attention of the UVAM which guides attention toward pre-learned objects. Weight perturbation-based learning of the HE ensures high attention precision through online adaptation. The SIFT recognition is accelerated by an optimized array of 420-way SIMD Vector Processing Elements, 32 MIMD Scalar Processing Elements, and 1 Feature Matching Processor. When processing 30 fps 640 × 480 video, the 50 mm2 object recognition processor implemented in a 0.13 μm process achieves 246 EGOPS/W, which is 46 % higher than the previous work. The average power consumption is only 345 mW. View full abstract»

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  • A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS Technology

    Publication Year: 2011 , Page(s): 52 - 63
    Cited by:  Papers (8)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2274 KB) |  | HTML iconHTML  

    A 4 Mb embedded phase change memory macro has been developed in a 90 nm 6-ML CMOS technology. The storage element has been integrated using 3 additional masks with respect to process baseline. The cell selector is implemented by a standard LV nMOS device, achieving a cell size of 0.29 μm2. A dual-voltage row decoder and a double-path column decoder are introduced, enabling a completely low voltage read operation. A 20b-parallelism write scheme is embedded in the digital controller in order to maximize throughput. In alternative, a power-saving low-parallelism write algorithm can be employed. The macro features a 1.2 V 12 ns read access time and a write throughput of 1 MB/s. Set and reset current distributions showing a good read window are presented and robust reliability results are demonstrated. View full abstract»

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  • A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache

    Publication Year: 2011 , Page(s): 64 - 75
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2422 KB) |  | HTML iconHTML  

    A 1.35 ns random access and 1.7 ns-random-cycle SOI embedded-DRAM macro has been developed for the POWER7™ high-performance microprocessor. The macro employs a 6 transistor micro sense-amplifier architecture with extended precharge scheme to enhance the sensing margin for product quality. The detailed study shows a 67% bit-line power reduction with only 1.7% area overhead, while improving a read zero margin by more than 500ps. The array voltage window is improved by the programmable BL voltage generator, allowing the embedded DRAM to operate reliably without constraining of the microprocessor voltage supply windows. The 2.5nm gate oxide transistor cell with deep-trench capacitor is accessed by the 1.7 V wordline high voltage (VPP) with V WL low voltage (VWL), and both are generated internally within the microprocessor. This results in a 32 MB on-chip L3 on-chip-cache for 8 cores in a 567 mm POWER7™ die. View full abstract»

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  • A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation

    Publication Year: 2011 , Page(s): 76 - 84
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1834 KB) |  | HTML iconHTML  

    SRAM bitcell design margin continues to shrink due to random and systematic process variation in scaled technologies and conventional SRAM faces a challenge in realizing the power and density benefits of technology scaling. Smart and adaptive assist circuits can improve design margins while satisfying SRAM power and performance requirements in scaled technologies. This paper introduces an adaptive, dynamic SRAM word-line under-drive (ADWLUD) scheme that uses a bitcell-based sensor to dynamically optimize the strength of WLUD for each die. The ADWLUD sensor enables 130 mV reduction in SRAM Vccmin while increasing frequency yield by 9% over conventional SRAM without WLUD. The sensor area overhead is limited to 0.02% and power overhead is 2% for a 3.4 Mb SRAM array. View full abstract»

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  • A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS

    Publication Year: 2011 , Page(s): 85 - 96
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2374 KB) |  | HTML iconHTML  

    An 8T SRAM fabricated in 45 nm SOI CMOS exhibits voltage scalable operation from 1.2V down to 0.57V with access times from 400 ps to 3.4 ns. Timing variation and the challenge of low voltage operation are addressed with an AC-coupled sense amplifier. An area efficient data path is achieved with a regenerative global bitline scheme. Finally, a data retention voltage sensor has been developed to predict the mismatch-limited minimum standby voltage without corrupting the contents of the memory. View full abstract»

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  • A 32-Gb MLC NAND Flash Memory With Vth Endurance Enhancing Schemes in 32 nm CMOS

    Publication Year: 2011 , Page(s): 97 - 106
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3997 KB) |  | HTML iconHTML  

    Novel program and read schemes are presented to break barriers in scaling of NAND flash memory such as threshold voltage endurance from floating gate interference, and charge loss tolerance. To enhance threshold voltage endurance and charge loss tolerance, we introduced three schemes; MSB Re-PGM scheme, Moving Read scheme and Adaptive Code Selection scheme. Using the MSB Re-PGM scheme, threshold voltage distribution width is improved about 200 mV. The PGM throughput is enhanced from 1500 μs to 1250 μs. With the Moving Read scheme about half order of UBER is improved with 10 bit ECC. Also, Adaptive Code Selection scheme are used to decrease a current consumption. There is 5.5% current reduction. With these techniques, 32-Gb MLC NAND flash memory has been fabricated using a 32 nm CMOS process technology. Its program throughput reaches 13.0 MB/s at a multi-plane program operation with cache operation keeping a desirable threshold voltage distribution. View full abstract»

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  • A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

    Publication Year: 2011 , Page(s): 107 - 118
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3213 KB) |  | HTML iconHTML  

    This paper describes a 1 Gbit GDDR5 SDRAM with enhanced bank access flexibility for efficient data transfer in 7 Gb/s per pin IO bandwidth. The enhanced flexibility is achieved by elimination of bank group restriction and reduction of bank to bank active time to 2.5 ns. The effectiveness of these key features is verified by system model simulation including memory and its controller. To realize the enhanced bank access flexibility, this DRAM employs the following techniques: skewed control logic, PVT variation compensated IO sense amplifier with auto calibration by replica impedance monitor, FIFO based BLSA enable signal generator, low latency VPP generator and active jitter canceller. This GDDR5 SDRAM was fabricated in 50 nm standard DRAM process in 61.6 die area and operates with 1.5 V power supply. View full abstract»

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  • A Family of 32 nm IA Processors

    Publication Year: 2011 , Page(s): 119 - 130
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2589 KB) |  | HTML iconHTML  

    Westmere is the latest IA processor family for mobile, desktop and server market segments, implemented on Intel's second-generation high-k metal gate 32 nm process. Westmere not only increases core count, cache size, and frequency within the previous generation's power envelope, it also provides further improvements in power efficiency, feature set, and support for combo DDR3 and low voltage DDR3 despite using a thin gate technology. View full abstract»

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  • A 40 nm 16-Core 128-Thread SPARC SoC Processor

    Publication Year: 2011 , Page(s): 131 - 144
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2946 KB) |  | HTML iconHTML  

    This fourth generation UltraSPARC T3 SoC processor implements sixteen 8-threaded SPARC cores to double on-chip thread count and throughput performance over its previous generation. It enhances glueless scalability to enable up to 512 threads in a 4-way system. A 16-Bank 6 MB L2 Cache, a 512 GB/s hierarchical crossbar and a 312-lane SerDes I/O of 2.4 Tb/s support the bandwidth required by the large number of threads. This SoC processor integrates the memory controller, PCIE 2.0, 10 Gb Ethernet ports, and required cache coherency support in multi-chip configurations. Multiple clock and power domains are used to optimize performance and power for the SoC components. Extensive power management features, from architecture to circuit techniques, optimize both active and idle power. The 377 die includes 1 billion transistors in a flip-chip ceramic package with 2117 pins. The chip is fabricated in TSMC's 40 nm high-performance process with 11 Cu metals and four transistor types. View full abstract»

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  • POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor

    Publication Year: 2011 , Page(s): 145 - 161
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3388 KB) |  | HTML iconHTML  

    This paper gives an overview of the latest member of the POWER™ processor family, POWER7™. Eight quad-threaded cores, operating at frequencies up to 4.14 GHz, are integrated together with two memory controllers and high speed system links on a 567 mm die, employing 1.2B transistors in a 45 nm CMOS SOI technology with 11 layers of low-k copper wiring. The technology features deep trench capacitors which are used to build a 32 MB embedded DRAM L3 based on a 0.067 m DRAM cell. The functionally equivalent chip transistor count would have been over 2.7B if the L3 had been implemented with a conventional 6 transistor SRAM cell. (A detailed paper about the eDRAM implementation will be given in a separate paper of this Journal). Deep trench capacitors are also used to reduce on-chip voltage island supply noise. This paper describes the organization of the design and the features of the processor core, before moving on to discuss the circuits used for analog elements, clock generation and distribution, and I/O designs. The final section describes the details of the clocked storage elements, including special features for test, debug, and chip frequency tuning. View full abstract»

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  • An x86-64 Core in 32 nm SOI CMOS

    Publication Year: 2011 , Page(s): 162 - 172
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2244 KB) |  | HTML iconHTML  

    This paper describes the 32 nm implementation of an AMD x86-64 core. It occupies 9.69 mm2, contains more than 35 million transistors (excluding L2 cache), and operates at frequencies in excess of 3 GHz. This AMD chip is fabricated in Global Foundries' 32 nm SOI and uses high-K metal gate technology. The process uses dual strain liners and eSiGe (embedded Silicon Germanium) to improve performance. Transistors are fabricated in various threshold voltages and lengths to facilitate performance/leakage tradeoffs. The core incorporates numerous design and power improvements to enable an operating range of 2.5 W to 25 W and a near zero-power gated state, which makes the core well-suited to a broad range of mobile and desktop products including multicore SOC designs. View full abstract»

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  • A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

    Publication Year: 2011 , Page(s): 173 - 183
    Cited by:  Papers (97)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2464 KB) |  | HTML iconHTML  

    This paper describes a multi-core processor that integrates 48 cores, 4 DDR3 memory channels, and a voltage regulator controller in a 64 2D-mesh network-on-chip architecture. Located at each mesh node is a five-port virtual cut-through packet-switched router shared between two IA-32 cores. Core-to-core communication uses message passing while exploiting 384 KB of on-die shared memory. Fine grain power management takes advantage of 8 voltage and 28 frequency islands to allow independent DVFS of cores and mesh. At the nominal 1.1 V supply, the cores operate at 1 GHz while the 2D-mesh operates at 2 GHz. As performance and voltage scales, the processor dissipates between 25 W and 125 W. The processor is implemented in 45 nm Hi-K CMOS and has 1.3 billion transistors. View full abstract»

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  • Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor

    Publication Year: 2011 , Page(s): 184 - 193
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2518 KB) |  | HTML iconHTML  

    In this paper, we present measured within-die core-to-core Fmax and leakage variation data for an 80-core processor in 65 nm CMOS and 1) populate a parameterized energy/performance model to determine the most energy-efficient operating point for a workload; 2) examine impacts of per-core clock and power gating on optimal dynamic voltage-frequency-core scaling (DVFCS) operating points; and 3) compare improvements in energy efficiency achievable by variation-aware DVFCS and core mapping on Single-Voltage/Multiple-Frequency (SVMF), Multiple-Voltage/Single-Frequency (MVSF) and Multiple-Voltage/Multiple-Frequency (MVMF) designs. Variation-aware DVFS with optimal core mapping is shown to improve energy efficiency 6%-35% across a range of compute/communication activity workloads. A new dynamic thread hopping scheme boosts performance by 5%-10% or energy efficiency by 20%-60%. View full abstract»

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  • A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance

    Publication Year: 2011 , Page(s): 194 - 208
    Cited by:  Papers (56)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2716 KB) |  | HTML iconHTML  

    A 45 nm microprocessor core integrates resilient error-detection and recovery circuits to mitigate the clock frequency (FCLK) guardbands for dynamic parameter variations to improve throughput and energy efficiency. The core supports two distinct error-detection designs, allowing a direct comparison of the relative trade-offs. The first design embeds error-detection sequential (EDS) circuits in critical paths to detect late timing transitions. In addition to reducing the Fclk guardbands for dynamic variations, the embedded EDS design can exploit path-activation rates to operate the microprocessor faster than infrequently-activated critical paths. The second error-detection design offers a less-intrusive approach for dynamic timing-error detection by placing a tunable replica circuit (TRC) per pipeline stage to monitor worst-case delays. Although the TRCs require a delay guardband to ensure the TRC delay is always slower than critical-path delays, the TRC design captures most of the benefits from the embedded EDS design with less implementation overhead. Furthermore, while core min-delay constraints limit the potential benefits of the embedded EDS design, a salient advantage of the TRC design is the ability to detect a wider range of dynamic delay variation, as demonstrated through low supply voltage (VCC) measurements. Both error-detection designs interface with error-recovery techniques, enabling the detection and correction of timing errors from fast-changing variations such as high-frequency VCC droops. The microprocessor core also supports two separate error-recovery techniques to guarantee correct execution even if dynamic variations persist. The first technique requires clock control to replay errant instructions at 1/2FCLK. In comparison, the second technique is a new multiple-issue instruction replay design that corrects errant instructions with a lower performance penalty and without requiring clock control. Silico- - n measurements demonstrate that resilient circuits enable a 41% throughput gain at equal energy or a 22% energy reduction at equal throughput, as compared to a conventional design when executing a benchmark program with a 10% VCC droop. In addition, the microprocessor includes a new adaptive clock control circuit that interfaces with the resilient circuits and a phase-locked loop (PLL) to track recovery cycles and adapt to persistent errors by dynamically changing Fclk f°Γ maximum efficiency. View full abstract»

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  • A 30 \mu W Analog Signal Processor ASIC for Portable Biopotential Signal Monitoring

    Publication Year: 2011 , Page(s): 209 - 223
    Cited by:  Papers (33)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3371 KB) |  | HTML iconHTML  

    This paper presents the design and implementation of an analog signal processor (ASP) ASIC for portable ECG monitoring systems. The ASP ASIC performs four major functionalities: 1) ECG signal extraction with high resolution, 2) ECG signal feature extraction, 3) adaptive sampling ADC for the compression of ECG signals, 4) continuous-time electrode-tissue impedance monitoring for signal integrity monitoring. These functionalities enable the development of wireless ECG monitoring systems that have significantly lower power consumption yet that are more capable than their predecessors. The ASP has been implemented in 0.5 μm CMOS process and consumes 30 μW from a 2 V supply. The noise density of the ECG readout channel is 85 nV/√Hz and the CMRR is better that 105 dB. The adaptive sampling ADC is capable of compressing the ECG data by a factor of 7 and the heterodyne chopper readout extracts the features of the ECG signals. Combination of these two features leads to a factor 4 reduction in the power consumption of a wireless ECG monitoring system. Furthermore, the proposed continuous-time impedance monitoring circuit enables the monitoring of the signal integrity. View full abstract»

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  • A 76 dB \Omega 1.7 GHz 0.18 \mu m CMOS Tunable TIA Using Broadband Current Pre-Amplifier for High Frequency Lateral MEMS Oscillators

    Publication Year: 2011 , Page(s): 224 - 235
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1843 KB) |  | HTML iconHTML  

    This paper reports on the design and characterization of a high-gain tunable transimpedance amplifier (TIA) suitable for gigahertz oscillators that use high-Q lateral micromechanical resonators with large motional resistance and large shunt parasitic capacitance. The TIA consists of a low-power broadband current pre-amplifler combined with a current-to-voltage conversion stage to boost the input current before delivering it to feedback voltage amplifiers. Using this approach, the TIA achieves a constant gain of 76 dB-Ohm up to 1.7 GHz when connected to a 2 pF load at the input and output with an input-referred noise below 10 pA/√(Hz) in the 100 MHz to 1 GHz range. The TIA is fabricated in a 1P6M 0.18 μm CMOS process and consumes 7.2 mW. To demonstrate its performance in high frequency lateral micromechanical oscillator applications, the TIA is wirebonded to a 724 MHz high-motional resistance (Qunloaded ≈ 2000, Rm ≈ 750 Ω, CP ≈ 2 pF) and a 1.006 GHz high-parasitic (Qunloaded ≈ 7100, Rm ≈ 150 Ω, CP ≈ 3.2 pF) AIN-on-Silicon resonator. The 724 MHz and 1.006 GHz oscillators achieve phase-noise better than -87 dBc/Hz and -94 dBc/Hz @ 1 kHz offset, respectively, with a floor around -154 dBc/Hz. The 1.006 GHz oscillator achieves the highest reported figure of merit (FoM) among lateral piezoelectric micromechanical oscillators and meets the phase-noise requirements for most 2G and 3G cellular standards including GSM 900 MHz, GSM 1800 MHz, and HSDPA. View full abstract»

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  • A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel \Delta \Sigma ADC Architecture

    Publication Year: 2011 , Page(s): 236 - 247
    Cited by:  Papers (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2188 KB) |  | HTML iconHTML  

    This paper presents a 2.1 M pixel, 120 frame/s CMOS image sensor with column-parallel delta-sigma (ΔΣ) ADC architecture. The use of a second-order ΔΣ ADC improves the conversion speed while reducing the random noise (RN) level as well. The ΔΣ ADC employing an inverter-based ΔΣ modulator and a compact decimation filter is accommodated within a fine pixel pitch of 2.25-μm and improves energy efficiency while providing a high frame-rate of 120 frame/s. A prototype image sensor has been fabricated with a 0.13-μm CMOS process. Measurement results show a RN of 2.4 erms- and a dynamic range of 73 dB. The power consumption of the prototype image sensor is only 180 mW. This work achieves the energy efficiency of 1.7 e-·nJ. View full abstract»

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  • A Range Image Sensor Based on 10- \mu{\hbox {m}} Lock-In Pixels in 0.18- \mu m CMOS Imaging Technology

    Publication Year: 2011 , Page(s): 248 - 258
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3104 KB) |  | HTML iconHTML  

    This paper presents the design and characterization of a lock-in pixel array based on a buried channel photo-detector aimed at time-of-flight range imaging. The proposed photo-demodulator has been integrated in a 10-μm pixel pitch with a fill factor of 24%, and is capable of a maximum demodulation frequency of 50 MHz with a contrast of 29.5%. The sensor has been fabricated in a 0.18-μm CMOS imaging technology and assembled in a range camera system setup. The system provides a stream of three-dimensional images at 5-20 fps on a 3-6 m range, with a linearity error lower than 0.7% and a repeatability of 5-16 cm, while the best achievable precision is 2.7 cm at a 50-MHz modulation frequency. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan