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# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Displaying Results 1 - 23 of 23
• ### Table of contents

Publication Year: 2011, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2011, Page(s): C2
| PDF (40 KB)
• ### Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops

Publication Year: 2011, Page(s):1 - 9
Cited by:  Papers (14)  |  Patents (5)
| | PDF (601 KB) | HTML

A novel explicit-pulsed dual-edge triggered sense-amplifier flip-flop (DET-SAFF) for low-power and high-performance applications is presented in this paper. By incorporating the dual-edge triggering mechanism in the new fast latch and employing conditional precharging, the DET-SAFF is able to achieve low-power consumption that has small delay. To further reduce the power consumption at low switchi... View full abstract»

• ### Quasi-Static Voltage Scaling for Energy Minimization With Time Constraints

Publication Year: 2011, Page(s):10 - 23
Cited by:  Papers (5)
| | PDF (777 KB) | HTML

Supply voltage scaling and adaptive body biasing (ABB) are important techniques that help to reduce the energy dissipation of embedded systems. This is achieved by dynamically adjusting the voltage and performance settings according to the application needs. In order to take full advantage of slack that arises from variations in the execution time, it is important to recalculate the voltage (perfo... View full abstract»

• ### SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage

Publication Year: 2011, Page(s):24 - 32
Cited by:  Papers (31)  |  Patents (4)
| | PDF (1614 KB) | HTML

Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write operation without using any on-chip or off-... View full abstract»

• ### Efficient Pattern Matching Algorithm for Memory Architecture

Publication Year: 2011, Page(s):33 - 41
Cited by:  Papers (9)
| | PDF (609 KB) | HTML

Network intrusion detection system is used to inspect packet contents against thousands of predefined malicious or suspicious patterns. Because traditional software alone pattern matching approaches can no longer meet the high throughput of today's networking, many hardware approaches are proposed to accelerate pattern matching. Among hardware approaches, memory-based architecture has attracted a ... View full abstract»

• ### A New Compact SD2 Positive Integer Triangular Array Division Circuit

Publication Year: 2011, Page(s):42 - 51
| | PDF (745 KB) | HTML

Division is the highest latency arithmetic operation in present digital architectures and high-performance computing systems; as such drives the demand for efficient hardware division units. Accordingly, this paper proposes a novel architecture for a nonrestoring divisor based on the radix-2 signed-digit (SD2) representation. This notation has been chosen to achieve fast computation, as proposed b... View full abstract»

• ### High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications

Publication Year: 2011, Page(s):52 - 60
Cited by:  Papers (31)
| | PDF (919 KB) | HTML

The fixed-width multiplier is attractive to many multimedia and digital signal processing systems which are desirable to maintain a fixed format and allow a little accuracy loss to output data. This paper presents the design of high-accuracy fixed-width modified Booth multipliers. To reduce the truncation error, we first slightly modify the partial product matrix of Booth multiplication and then d... View full abstract»

• ### A 470-$mu{hbox {W}}$ 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider With an In-Phase Dual-Input Injection Scheme

Publication Year: 2011, Page(s):61 - 70
Cited by:  Papers (6)  |  Patents (1)
| | PDF (1712 KB) | HTML

This paper presents a digitally controlled injection-locked multimodulus frequency divider (ILMFD) based on a ring-oscillator using inverter chains for a small area and low power consumption. In the proposed ILMFD, division ratios of 2, 3, 4, 5 and 6 are achieved by using a programmable delay line that changes the self-oscillation frequency of the ring-oscillator. The locking range of the proposed... View full abstract»

• ### Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design

Publication Year: 2011, Page(s):71 - 84
Cited by:  Papers (9)
| | PDF (1047 KB) | HTML

Field-programmable gate arrays (FPGAs) are used in a variety of markets that have differing cost, performance and power consumption requirements. While it would be ideal to serve all these markets with a single FPGA family, the diversity in the needs of these markets means that generally more than one family is appropriate. Consequently, FPGA vendors have moved to provide a diverse set of families... View full abstract»

• ### A Lightweight High-Performance Fault Detection Scheme for the Advanced Encryption Standard Using Composite Fields

Publication Year: 2011, Page(s):85 - 91
Cited by:  Papers (26)
| | PDF (245 KB) | HTML

The faults that accidently or maliciously occur in the hardware implementations of the Advanced Encryption Standard (AES) may cause erroneous encrypted/decrypted output. The use of appropriate fault detection schemes for the AES makes it robust to internal defects and fault attacks. In this paper, we present a lightweight concurrent fault detection scheme for the AES. In the proposed approach, the... View full abstract»

• ### Accurate Timing and Noise Analysis of Combinational and Sequential Logic Cells Using Current Source Modeling

Publication Year: 2011, Page(s):92 - 103
Cited by:  Papers (8)  |  Patents (1)
| | PDF (952 KB) | HTML

A current source model (CSM) for CMOS logic cells is presented, which can be used for accurate noise and delay analysis in CMOS VLSI circuits. CS modeling is broadly considered as the method of choice for modern static timing and noise analysis tools. Unfortunately, the existing CSMs are only applicable to combinational logic cells. In addition to multistage logic nature of the sequential cells, t... View full abstract»

• ### Location Cache Design and Performance Analysis for Chip Multiprocessors

Publication Year: 2011, Page(s):104 - 117
Cited by:  Papers (4)
| | PDF (1651 KB) | HTML

Recent research at Intel suggests that chips with hundreds of processor cores are possible in the not-so-distant future. As the number of cores grows, so does the size of the cache systems required to allow them to operate efficiently. Caches have grown to consume a significant percentage of the power utilized by a processor. In this research, we extend the concept of location cache to support chi... View full abstract»

• ### A Novel Asynchronous Pixel for an Energy Harvesting CMOS Image Sensor

Publication Year: 2011, Page(s):118 - 129
Cited by:  Papers (22)
| | PDF (1596 KB) | HTML

This paper proposes a novel energy harvesting technique based on an asynchronous pixel structure and an efficient energy generation scheme, referred to as avalanche energy generation (AEG). The key idea behind using an asynchronous type of pixel is to lower the power consumption by enabling only active pixels to be read-out after which they enter into a power generation mode. In this mode, the on-... View full abstract»

• ### ${rm C}Delta{rm IDDQ}$: Improving Current-Based Testing and Diagnosis Through Modified Test Pattern Generation

Publication Year: 2011, Page(s):130 - 141
Cited by:  Papers (3)
| | PDF (1128 KB) | HTML

This paper presents a novel approach to extending the life of current-based test techniques for the detection and diagnosis of bridging defects. Called CΔIDDQ (Complementary ΔIDDQ), this approach combines a modified test pattern generation with a simple post-processing of IDDQ measurements (namely additions and subtractions) such that the resulting measurement combination ... View full abstract»

• ### Fixed-State Tests for Delay Faults in Scan Designs

Publication Year: 2011, Page(s):142 - 146
Cited by:  Papers (3)
| | PDF (206 KB) | HTML

One of the methods to reduce the power dissipation during scan shifting is based on holding the state inputs to the combinational logic of a circuit constant for the duration of a scan operation. We note that this method also allows a new type of two-pattern scan-based tests to be applied. We refer to these tests as fixed-state tests. These tests have several properties that make them effective as... View full abstract»

• ### Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating

Publication Year: 2011, Page(s):146 - 151
Cited by:  Papers (2)
| | PDF (290 KB) | HTML

The capability of accurately estimating an upper bound of the maximum current drawn by a digital macroblock from the ground or power supply line constitutes a major asset of automatic power-gating flows. In fact, the maximum current information is essential to properly size the sleep transistor in such a way that speed degradation and signal integrity violations are avoided. Loose upper bounds can... View full abstract»

• ### Multi-Threshold Voltage FinFET Sequential Circuits

Publication Year: 2011, Page(s):151 - 156
Cited by:  Papers (17)
| | PDF (598 KB) | HTML

New multi threshold voltage (multi-Vth) brute-force FinFET sequential circuits with independent-gate bias, work-function engineering, and gate-drain/source overlap engineering techniques are presented in this paper. The total active mode power consumption, the clock power, and the average leakage power of the multi-Vth sequential circuits are reduced by up to 55%, 29%, and 53... View full abstract»

• ### Channel Estimator and Aliasing Canceller for Equalizing and Decoding Non-Cyclic Prefixed Single-Carrier Block Transmission via MIMO-OFDM Modem

Publication Year: 2011, Page(s):156 - 160
| | PDF (1435 KB) | HTML

Without a cyclic prefix (CP), most single-carrier (SC) transmissions can not adopt frequency-domain equalizer (FDE) directly. This work utilizes frequency-domain channel estimator (FD-CE) and decision-feedback aliasing canceller (DF-AC) to produce single-FFT SC-FDE. In this way, non-CP single-carrier block transmission (SCBT) can be decoded using sphere decoder of MIMO-OFDM modems to support multi... View full abstract»

• ### Reconfigurable SRAM Architecture With Spatial Voltage Scaling for Low Power Mobile Multimedia Applications

Publication Year: 2011, Page(s):161 - 165
Cited by:  Papers (15)
| | PDF (836 KB) | HTML

This paper presents a dynamically reconfigurable SRAM array for low-power mobile multimedia application. The proposed structure use a lower voltage for cells storing low-order bits and a nominal voltage for cells storing higher order bits. The architecture allows reconfigure the number of bits in the low-voltage mode to change the error characteristics of the array in run-time. Simulations in pred... View full abstract»

• ### A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme

Publication Year: 2011, Page(s):165 - 170
Cited by:  Papers (16)
| | PDF (847 KB) | HTML

In this brief, we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). This ADPLL achieves low output clock jitter by a number of schemes. First, the phase is locked quickly through a predictive phase-locking scheme. Then, the jitter is further reduced by a suppressive digital loop filter. Finally, an interpolation-based locking scheme is utilized to enhance the resolution of... View full abstract»

• ### IEEE copyright form

Publication Year: 2011, Page(s):171 - 172
| PDF (1065 KB)
• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

Publication Year: 2011, Page(s): C3
| PDF (27 KB)

## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu