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Electron Device Letters, IEEE

Issue 1 • Date Jan. 2011

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Displaying Results 1 - 25 of 43
  • Table of contents

    Publication Year: 2011 , Page(s): C1 - 2
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    Freely Available from IEEE
  • IEEE Electron Device Letters publication information

    Publication Year: 2011 , Page(s): C2
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  • On the RF Properties of Weakly Saturated SiGe HBTs and Their Potential Use in Ultralow-Voltage Circuits

    Publication Year: 2011 , Page(s): 3 - 5
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (387 KB) |  | HTML iconHTML  

    We investigate, for the first time, the feasibility of operating silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) in a weakly saturated bias regime to enable ultralow-voltage RF front-end design. Measured dc, ac, and RF characteristics of third-generation high-performance SiGe HBTs operating in weak saturation are presented. Robust RF operation of 0.12 × 6.0 μm2 SiGe HBTs are demonstrated in a common-emitter configuration at collector-to-emitter voltages above 0.15 V. A noise figure of 1.33 dB and an input third-order intercept point above -8 dBm for a 3-GHz input tone are achieved at 0.30 V. These results have potential implications for RF circuits used in severely power-constrained systems. View full abstract»

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  • Computational Study of Edge Configuration and Quantum Confinement Effects on Graphene Nanoribbon Transport

    Publication Year: 2011 , Page(s): 6 - 8
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (306 KB) |  | HTML iconHTML  

    We investigated edge configuration and quantum confinement effects on electron transport in armchair-edged graphene nanoribbons (A-GNRs) by using a computational approach. We found that the edge bond relaxation has a significant influence not only on the bandgap energy but also on the electron effective mass. We also found that A-GNRs with N = 3m family (N is the number of atoms in its transverse direction, and m is a positive integer) exhibits smaller effective mass by comparing it at the same bandgap energy. As a result, A-GNRs with N = 3m family are found to be favorable for use in channels of field-effect transistors. View full abstract»

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  • An Octagonal Dual-Gate Transistor With Enhanced and Adaptable Low-Frequency Noise

    Publication Year: 2011 , Page(s): 9 - 11
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (525 KB) |  | HTML iconHTML  

    As the low-frequency noise of a transistor grows nonnegligible in advanced technologies, the possibility of using noise for computation is becoming an alternative, receiving more and more attention. The ability to control the noise level would further enrich the flexibility of the circuit design. Therefore, this letter presents a dual-gate field-effect transistor in an octagonal shape. By changing the voltage of an extra gate above the shallow trench isolation, the transistor is able to adapt its low-frequency noise over several decades and in a power-efficient manner. The octagonal geometry further makes sufficient a voltage range from 0 to 5 V for the noise adaptation. Moreover, the transistor is fabricated with the standard CMOS logic process without additional masks. All the features underpin the development of large-scale noisy computation in integrated circuits. View full abstract»

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  • Second Harmonic Generation Indicates a Better Si/Ge Interface Quality for Higher Temperature and With \hbox {N}_{2} Rather Than With \hbox {H}_{2} as the Carrier Gas

    Publication Year: 2011 , Page(s): 12 - 14
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (370 KB) |  | HTML iconHTML  

    In order for germanium (Ge) to replace silicon in advanced MOSFET channels, proper passivation of Ge is required. For this purpose, an ultrathin epitaxial Si cap was grown on Ge(001), and we applied second harmonic generation (SHG) in order to probe the Si/Ge interface quality. SHG indicates a better interface quality for a growth temperature of 500°C rather than 450°C. Similarly, a better quality of the interface is observed upon replacing the conventional H2 carrier gas with N2. Additionally, from the SHG signal, we were able to extract both the thickness of the native SiO2 layer (~4 monolayers (MLs)] and the thickness of the strained Si layer (relaxation at ~12 MLs). These results are important for building Ge-based electronic components. View full abstract»

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  • Integration of \hbox {LaLuO}_{3} (\kappa \sim \hbox {30}) as High- \kappa Dielectric on Strained and Unstrained SOI MOSFETs With a Replacement Gate Process

    Publication Year: 2011 , Page(s): 15 - 17
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (453 KB) |  | HTML iconHTML  

    The integration of lanthanum lutetium oxide (LaLuO3) with a n value of 30 is, for the first time, demonstrated on strained and unstrained SOI n/p-MOSFETs as a gate dielectric with a full replacement gate process. The LaLuO3/Si interface showed a very thin silicate/SiO2 interlayer with a Dit level of 4.5 × 1011 (eV · cm2)-1. Fully depleted n/p-MOSFETs with LaLuO3/TiN gate stacks indicated very good performance with steep subthreshold slopes of ~70 mV/dec and high Ion/Ioff ratios. In addition, strained SOI shows enhanced electron mobilities with a factor of 1.7 compared to SOI. Both electron and hole mobilities for LaLuO3 on SOI are similar to the mobilities in reported Hf-based high-κ devices. View full abstract»

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  • Impact of Quantum Confinement on Short-Channel Effects for Ultrathin-Body Germanium-on-Insulator MOSFETs

    Publication Year: 2011 , Page(s): 18 - 20
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (405 KB) |  | HTML iconHTML  

    This letter investigates the impact of quantum confinement (QC) on the short-channel effect (SCE) of ultrathin-body (UTB) and thin-buried-oxide germanium-on-insulator (GeOI) MOSFETs using an analytical solution of Schrödinger equation verified with TCAD simulation. Our study indicates that, although the QC effect increases the threshold voltage (Vth) roll-off when the channel thickness (Tch) is larger than a critical value (Tch,crit), it may decrease the Vth roll-off of GeOI MOSFETs when the Tch is smaller than Tch,crit. Since Ge and Si channels exhibit different degrees of confinement and Tch,crit, the impact of QC must be considered when one-to-one comparisons between UTB GeOI and Si-on-insulator MOSFETs regarding the SCE are made. View full abstract»

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  • A Degenerately Doped \hbox {In}_{0.53}\hbox {Ga}_{0.47} \hbox {As} Bipolar Junction Transistor

    Publication Year: 2011 , Page(s): 21 - 23
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB) |  | HTML iconHTML  

    An InGaAs bipolar junction transistor having degenerately doped base and emitter layers is reported. The high emitter efficiency is attributed to the asymmetry between the density of states of the conduction and valence bands. A high-frequency transistor having base and emitter metals simultaneously deposited on the emitter layer is demonstrated. The base contact backward diode resistance was 125 Ω · μm2. View full abstract»

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  • InGaAs/InP DHBTs in a Dry-Etched Refractory Metal Emitter Process Demonstrating Simultaneous f_{\tau }/f_{\max } \sim \hbox {430/800} \hbox {GHz}

    Publication Year: 2011 , Page(s): 24 - 26
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (302 KB) |  | HTML iconHTML  

    Abstract-We report an InPZIn0.53Ga0.47As/InP double heterojunction bipolar transistor (DHBT) demonstrating simultaneous 430-GHz fτ and 800-GHz fmax. The devices were fabricated using a triple mesa process with dry-etched refractory metals for emitter contact formation. The devices incorporate a 30-nm-thick InP emitter semiconductor which enables a wet-etch emitter process demonstrating 270-nm-wide emitter-base junctions. At peak RF performance, the device is operating at 30 mW/μm2 with Jc = 18.4 mA/μm2 and Vce = 1.64 V. The devices show a peak DC common-emitter current gain (β) ~ 20 and VBR,CEO = 2.5 V. View full abstract»

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  • GaN Single-Polarity Power Supply Bootstrapped Comparator for High-Temperature Electronics

    Publication Year: 2011 , Page(s): 27 - 29
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (431 KB) |  | HTML iconHTML  

    A high-performance bootstrapped comparator operating with a single-polarity power supply is demonstrated for GaN high-temperature electronics applications. The comparator features monolithically integrated enhancement-mode (E-mode) and depletion-mode (D-mode) AlGaN/GaN HEMTs. The tail current source uses an E-mode HEMT, enabling single-polarity power supply. The E-mode input stage could cover a wide voltage comparison range (from 1 to 6 V) while the bootstrapped loads are implemented with D-mode HEMTs. At room temperature, the comparator delivers a voltage gain as high as 79 V/V and a unity-gain bandwidth of 206 MHz. At 250 , a maximum voltage gain of 40 V/V and a unity-gain bandwidth of 84 MHz are obtained. View full abstract»

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  • Record Breakdown Voltage (2200 V) of GaN DHFETs on Si With 2- \mu\hbox {m} Buffer Thickness by Local Substrate Removal

    Publication Year: 2011 , Page(s): 30 - 32
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (311 KB) |  | HTML iconHTML  

    In this letter, we present a local substrate removal technology (under the source-to-drain region), reminiscent of through-silicon vias and report on the highest ever achieved breakdown voltage (VBD) of AlGaN/GaN/AlGaN double heterostructure FETs on a Si (111) substrate with only 2-μm-thick AlGaN buffer. Before local Si removal, VBD saturates at ~700 V at a gate-drain distance (LGD) ≥ 8 μm. However, after etching away the substrate locally, we measure a record VBD of 2200 V for the devices with LGD = 20 μm. Moreover, from Hall measurements, we conclude that the local substrate removal integration approach has no impact on the 2-D electron gas channel properties. View full abstract»

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  • Self-Aligned Technology for N-Polar GaN/Al(Ga)N MIS-HEMTs

    Publication Year: 2011 , Page(s): 33 - 35
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (357 KB) |  | HTML iconHTML  

    In this letter, we introduce a scalable self-aligned technology for N-polar GaN MIS-HEMTs which can be used to achieve significant improvement in device performance by minimizing the source and drain access resistances. The methodology consists of a refractory-metal gate-first process followed by the regrowth of polarization-doped graded InGaN and InN layers by plasma-assisted molecular-beam epitaxy. The regrowth has been optimized to achieve ohmic contact resistance as low as 23 Ω-μm to the N-face 2-D electron gas. Excellent maximum current of 1.4 A/mm and a very low on resistance of 590 Ω-μm was achieved at (VG - VT) = 6 V for LG = 500 nm. Peak transconductance of 343 mS/mm is also state of the art for the given gate length and aspect ratio. Excellent fT.LG product of 15.9 GHz-μm with minimal drain delay was also achieved for LG = 600 nm. View full abstract»

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  • Self-Aligned Top-Gate Coplanar a-Si:H Thin-Film Transistors With a \hbox {SiO}_{2} –Silicone Hybrid Gate Dielectric

    Publication Year: 2011 , Page(s): 36 - 38
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (404 KB) |  | HTML iconHTML  

    We have made self-aligned top-gate coplanar hydrogenated amorphous-silicon (a-Si:H) thin-film transistors using a SiO2-silicone hybrid material as the gate dielectric. The hybrid dielectric layer is 150 nm thick and separates a chromium gate electrode from nickel silicide source and drain. The nickel silicide is formed by rapid thermal reaction of a deposited nickel film with the underlying a-Si:H. The electron field-effect mobility is ~1.0 cm2/V · s, the subthreshold slope is ~380 mV/decade, and the ON/OFF current ratio is ~105. The gate leakage current of ~10 pA across the 150-nm-thick hybrid dielectric is ~1/10 of that observed across the typical 300-nm-thick SiNx dielectric. The whole process needs only two masks. View full abstract»

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  • Design of Noncoplanar Diagonal Electrode Structure for Oxide Thin-Film Transistor

    Publication Year: 2011 , Page(s): 39 - 41
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (338 KB) |  | HTML iconHTML  

    The top-source noncoplanar diagonal electrode (TS-NDE) structure was fabricated and simulated with the oxide channel layer. The structure exhibits enhanced stability and low subthreshold swing with higher mobility than those of bottom-source electrode structure thin-film transistors (TFTs). Interestingly, in this highly stable TS-NDE, the current density was highly formed through the center of the active-channel region from top-source electrode to bottom-drain electrode in the thin-film layer due to the on-current state. In other words, the TS-NDE TFT is less affected by back-interface interferences, which are the main degradation factors in oxide TFTs due to the different current path. View full abstract»

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  • High-Performance Amorphous Indium Gallium Zinc Oxide Thin-Film Transistors With \hbox {HfO}_{x}\hbox {N}_{y}/\hbox {HfO}_{2}/\hbox {HfO}_{x}\hbox {N}_{y} Tristack Gate Dielectrics

    Publication Year: 2011 , Page(s): 42 - 44
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (326 KB) |  | HTML iconHTML  

    We have fabricated and investigated amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) by using HfOxNy/HfO2/HfOxNy (NON) as the gate dielectric. The NON tristack dielectric structure can increase the gate capacitance density, effectively improve interface properties of both the gate/dielectric and dielectric/active channels, suppress the charge trap density, and reduce the gate leakage. The α-IGZO TFT (W/L = 200/10 μm) with NON shows superior performance such as a saturation current of 0.33 mA, an ON/OFF-current ratio of 2.2 × 106, a saturation mobility of 10.2 cm2/V · s, a source/contact resistivity of 83 Ω · cm, a subthreshold swing of 0.13 V/dec, and enhanced stressing reliability. View full abstract»

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  • Light Trapping in Single Coaxial Nanowires for Photovoltaic Applications

    Publication Year: 2011 , Page(s): 45 - 47
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB) |  | HTML iconHTML  

    We report a strong enhancement of the light absorption in single coaxial nanowires (NWs) of Si core/dielectric shells. We have calculated the light absorption coefficient within the framework of the Lorenz-Mie light scattering theory and found out that it is greatly increased by effective light trapping in Si cores owing to dielectric shells, as compared to that in Si NWs. We show that the strong absorption of light stems mainly from off-resonance enhancement and also from resonance contribution. By optimally tuning the core radius, the shell thickness, and the shell refractive index, we have obtained ~102% increase of the photocurrent. View full abstract»

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  • Spherical Photovoltaic Device With Tailored Emitter Structure

    Publication Year: 2011 , Page(s): 48 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (257 KB) |  | HTML iconHTML  

    The design and fabrication of a spherical photovoltaic device with a tailored emitter are presented. A reactive ion etching process is used to thin the emitter, providing a progressively varying junction depth and sheet resistance along the spherical surface. The surface of the transparent emitter is passivated by a silicon nitride layer to improve the spectral response and the photocurrent. The tailored variation in emitter depth is also shown to provide a lower ohmic loss path for the current, compared to a uniformly thinned emitter, where the high sheet resistance adds to the series resistance, thereby degrading the fill factor of the device. View full abstract»

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  • Metal–Semiconductor–Metal Ultraviolet Photodetectors Based on Zinc-Oxide Colloidal Nanoparticles

    Publication Year: 2011 , Page(s): 51 - 53
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB) |  | HTML iconHTML  

    Metal-semiconductor-metal ultraviolet (UV) photodetectors were created with zinc-oxide colloidal nanoparticles coated with polyvinyl-alcohol. Gold-interdigitated finger contacts with different parameters were patterned on the nanoparticles by optical lithography. The photodetectors exhibited UV-photogenerated current to dark current ratios ranging from 3.85 × 106 to 1.34 × 108, depending on the finger parameters. The spectral responses demonstrate a 375 nm cutoff wavelength, with a peak responsivity of 731.42 A/W at 345 nm. View full abstract»

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  • A ZnO/ZnMgO Multiple-Quantum-Well Ultraviolet Random Laser Diode

    Publication Year: 2011 , Page(s): 54 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (342 KB) |  | HTML iconHTML  

    A ZnO/ZnMgO multiple-quantum-well ultraviolet (UV) random laser diode was fabricated on a commercially available n-type GaN wafer using a radio frequency magnetron sputtering system. The electroluminescence measurements revealed that the diode exhibited fairly pure UV random lasing centered at ~370 nm under sufficient forward bias at room temperature. The full-widths at half-maximum of the sharp lasing peaks are less than 0.4 nm. The device has a very low threshold current density of 4.7 A/cm2 and extremely weak visible emission. View full abstract»

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  • Low Write-Energy Magnetic Tunnel Junctions for High-Speed Spin-Transfer-Torque MRAM

    Publication Year: 2011 , Page(s): 57 - 59
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (255 KB) |  | HTML iconHTML  

    This letter presents energy-efficient MgO based magnetic tunnel junction (MTJ) bits for high-speed spin transfer torque magnetoresistive random access memory (STT-MRAM). We present experimental data illustrating the effect of device shape, area, and tunnel-barrier thickness of the MTJ on its switching voltage, thermal stability, and energy per write operation in the nanosecond switching regime. Finite-temperature micromagnetic simulations show that the write energy changes with operating temperature. The temperature sensitivity increases with increasing write pulsewidth and decreasing write voltage. We demonstrate STT-MRAM cells with switching energies of <;1 pJ for write times of 1-5 ns. View full abstract»

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  • A Novel Silicon-Embedded Coreless Inductor for High-Frequency Power Management Applications

    Publication Year: 2011 , Page(s): 60 - 62
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (318 KB) |  | HTML iconHTML  

    In this letter, a novel post-CMOS silicon-embedded coreless power inductor is proposed and demonstrated. The inductor is fabricated in the thick bottom layer of a silicon substrate and connected to the front side through vias opened in the thin top layer where control circuits can be fabricated for chip area saving. A 0.8- coreless inductor fabricated using this monolithic inductor technology shows a low dc resistance of 87 and an inductance of 13.1 nH with a quality factor of 3.9 at 100 MHz. A high inductor efficiency of 93% was estimated for 2.4-1.5-V 0.6-A power conversion at 100 MHz. This technology is very suitable for power-supply-on-chip applications. View full abstract»

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  • Improved Switching Uniformity and Speed in Filament-Type RRAM Using Lightning Rod Effect

    Publication Year: 2011 , Page(s): 63 - 65
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (423 KB) |  | HTML iconHTML  

    Improved switching uniformity and speed were demonstrated using a filament-type resistive memory. By using a gradual reset operation, a leaky high resistance, which has a smaller gap distance confirmed by C-AFM, was successfully obtained. The leaky high-resistance state shows significantly improved switching uniformity compared to the high-resistance state, which has a higher resistance than the leaky high-resistance state, because of the confinement of the randomly formed conducting filaments. A faster operation speed was achieved using the smaller gap distance. To confirm the improved switching speed, we monitored the real-time oscilloscope response. View full abstract»

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  • Evaluation of Cu Contamination at Backside Surface of Thinned Wafer in 3-D Integration by Transient-Capacitance Measurement

    Publication Year: 2011 , Page(s): 66 - 68
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (254 KB) |  | HTML iconHTML  

    The influence of Cu contamination at backside surface of a thinned wafer in three-dimensional LSI was electrically evaluated by capacitance-time (C-t) measurement. A MOS capacitor was fabricated using a thinned wafer of 50-μm thickness. The (C-t) curves of the MOS capacitor were severely degraded even after initial annealing at 300 °C for 5 min. It means that Cu atoms at the back surface reach the Si-SiO2 interface of the front surface, and the generation lifetime is significantly reduced. The quantitative relationship between the generation lifetime and surface concentration of Cu atom was evaluated. The (C-t) measurement is a highly promising method to electrically characterize the influence of Cu contamination on device reliability in fabricated LSI wafers. View full abstract»

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  • Performance Enhancement of On-Chip Inductors With Permalloy Magnetic Rings

    Publication Year: 2011 , Page(s): 69 - 71
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (485 KB) |  | HTML iconHTML  

    We demonstrate spiral inductors with continuous Permalloy ring structure at 100-μm scale, which achieve enhancements of sixfold in inductance and threefold in quality factor at frequencies as high as 200 MHz. The roll-off frequency is due to the eddy current loss in the conductive magnetic material. To reduce such loss and tune the permeability, the Permalloy film is laminated and split into bars. The dependence of the inductance and quality factor on permeability is further investigated. Different types of spiral inductors were fabricated with magnetic rings, helping shed light on optimization strategy. View full abstract»

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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Amitava Chatterjee