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Electron Devices, IEEE Transactions on

Issue 1 • Date Jan. 2011

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  • Table of contents

    Page(s): C1 - 2
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  • IEEE Transactions on Electron Devices publication information

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  • Changes in the Editorial Board

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  • Quantum Transport Simulation of Strain and Orientation Effects in Sub-20 nm Silicon-on-Insulator FinFETs

    Page(s): 4 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (890 KB) |  | HTML iconHTML  

    Quantum confinement in nanoscale MOSFETs based on silicon-on-insulator FinFET architecture will affect the effectiveness of strain engineering. This is because energy valley splitting due to quantum confinement may weaken the strain effect. In this paper, we investigate this phenomenon by an in-house quantum transport simulator, Schrödinger equation Monte Carlo in three dimensions, which can provide the quantum transport simulation of nanoscale 3-D MOSFET geometries such FinFETs, as well as take various scattering processes into account. Our simulation results indicate that the strain effect is more significant for devices with a channel orientation than those with a channel orientation. In addition, we also found that the strain effect is more notable when the scattering effect is considered in the quantum transport simulation. This result indicates that the scattering of hot carriers still plays a role in the carrier transport and, thus, the drain current of the nanoscale MOSFETs. View full abstract»

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  • A Program Disturb Model and Channel Leakage Current Study for Sub-20 nm nand Flash Cells

    Page(s): 11 - 16
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    We have developed a program-disturb model to characterize the channel potential of the program-inhibited string during NAND flash cell programming. This model includes cell-to-cell capacitances from 3-D technology computer-aided design simulation and leakage currents associated with the boosted channel. We studied the program-disturb characteristics of sub-30-nm NAND cells using a delayed programming pulse method. The simulation results agree with the experimental data very well and show quantitative impacts of junction leakage current, band-to-band tunneling (BTBT) current, Fowler-Nordheim tunneling current, and channel capacitance on the program disturb. We further discuss the cell-scaling trend and identify that the BTBT current can be a dominant mechanism for the program disturb of sub-20-nm NAND cells. View full abstract»

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  • Modeling and Performance Characterization of Double-Walled Carbon Nanotube Array Field-Effect Transistors

    Page(s): 17 - 25
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (943 KB) |  | HTML iconHTML  

    The performance prediction of double-walled carbon nanotube (DWCNT) array-built field-effect transistors (DWCNTFETs) is performed theoretically. The charge densities and surface potentials of double walls are solved in a self-consistent manner with the effects of wall screening among the DWCNT array treated appropriately. Some comparisons are made between our method and the nonequilibrium Green's function approach, with good agreement obtained. The influences of phonon scattering, doping resistances, Schottky barrier resistances, screening effects, and parasitic capacitances on DWCNTFET performance are examined in detail for different array geometries. It is found that, although its intrinsic channel part has no speed advantage over the single-walled counterpart, the overall speed performance can be better with low array densities and large diameters of the DWCNTs. The delay and cutoff frequency of the DWCNTFET can be decreased by 15% and increased by 30%, respectively. In particular, its better on current property can be utilized in the design of nanodevices with high-power-handling capability. View full abstract»

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  • Nanowire to Single-Electron Transistor Transition in Trigate SOI MOSFETs

    Page(s): 26 - 32
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    We investigate the effect of symmetrical geometrical constrictions on the electrical characteristics of ultrathin silicon-on-insulator nanowires with a trigate structure using a 3-D numerical quantum simulator. Introducing barriers at the source and drain junctions profoundly alter the device physics and a transition from 1-D to 0-D quantum behavior is observed. The constrictions create resonance levels in the channel region of nanowire due to confinement in the three directions of space, which, in turn, causes oscillation of the ID-VGS characteristic. Based on the observed characteristics, we derive a set of parameters that draws the line between 1-D and 0-D quantum behavior of silicon nanowire transistors. View full abstract»

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  • Annealing-Induced Changes in Electrical Characteristics of Al/Al-Rich \hbox {Al}_{2}\hbox {O}_{3}/p\hbox {-Si} Diodes

    Page(s): 33 - 38
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    Al-rich thin films are synthesized by radio-frequency magnetron sputtering, followed by thermal annealing at 500°C for different durations to form Al/Al-rich diodes. The annealing causes reactions at the Al-rich interface, leading to an increase in Al concentration in the interface region. As a result, the current conduction of the diode is significantly enhanced, which results in anomalous capacitance-voltage (C-V) characteristics. The anomalous behaviors can be eliminated by reconstructing the C-V curve based on a four-element circuit model. The resistance of the Al-rich layer extracted from the C-V reconstruction shows power-law voltage dependence correlated with the current-conduction measurement. View full abstract»

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  • Gate Direct Tunneling Current in Uniaxially Compressive Strained nMOSFETs: A Sensitive Measure of Electron Piezo Effective Mass

    Page(s): 39 - 45
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    Currently, both the band-structure calculation and the mobility measurement are used to assess the electron piezo-effective-mass coefficients in strained nMOSFETs. In this paper, we present a new experimental method through a fitting of the strain-altered electron gate direct tunneling current. The core of this method lies in the sensitivity of the direct tunneling to the position of the subband level in the presence of the electron piezo-effective-mass coefficients. First, a correction-coefficient generating expression is systematically constructed to compensate for the error in the subband levels due to the use of a triangular potential approximation. Then, with the known deformation potential constants and uniaxially compressive stress in the channel as inputs, a strain quantum simulator is carried out. The resulting gate direct tunneling current is used to fit experimental data, thus leading to the values of the piezo-effective-mass coefficients associated with the twofold and fourfold valleys. The comparison of the extracted piezo-effective-mass coefficients to those published in the literature is made. View full abstract»

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  • Large-Signal Model for Independent DG MOSFET

    Page(s): 46 - 52
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (606 KB) |  | HTML iconHTML  

    In this paper, we show the limitations of the traditional charge linearization techniques for modeling terminal charges of the independent double-gate metal-oxide-semiconductor field-effect transistors. Based on our recent computationally efficient Poisson solution for independent double gate transistors, we propose a new charge linearization technique to model the terminal charges and transcapacitances. We report two different types of quasistatic large-signal models for the long-channel device. In the first type, the terminal charges are expressed as closed-form functions of the source- and drain-end inversion charge densities and found to be accurate when the potential distribution at source end of the channel is hyperbolic in nature. The second type, which is found to be accurate in all regimes of operations, is based on the quadratic spline collocation technique and requires the input voltage equation to be solved two more times, apart from the source and drain ends. View full abstract»

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  • A New High-Density and Ultrasmall-Cell-Size Contact RRAM (CR-RAM) With Fully CMOS-Logic-Compatible Technology and Circuits

    Page(s): 53 - 58
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    A valid resistive dielectric film with excellent state switching is successfully demonstrated in a contact resistive RAM (CR-RAM) structure fabricated by 90-nm CMOS logic technology. This unique CR-RAM cell is realized by placing the RRAM material on top of the N+ silicon with a very small resistive switching area limited by the source line contact. In addition, the set and reset current of the new RRAM cell can be both well controlled and reduced by the choice of 1T + 1R structure. Furthermore, by adjusting operation conditions, an optimized high-speed and good-sensing margin cell is obtained with low levels of set and reset currents. Finally, the lower operation voltages and less current stress significantly improve data reliability, even after long-term high temperature and more than 1000 K cycling stresses. View full abstract»

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  • High-Mobility Ge N-MOSFETs and Mobility Degradation Mechanisms

    Page(s): 59 - 66
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    Ge N-MOSFETs have exhibited poor drive currents and low mobility, as reported by several different research groups in the past. The major mechanisms behind poor Ge NMOS performance have not been completely understood yet. In this paper, mechanisms responsible for poor Ge NMOS performance in the past are investigated with detailed gate dielectric stack characterizations and Hall mobility analysis. High source/drain (S/D) parasitic resistance, inversion charge loss due to trapping in the high-K gate dielectric, and high interface trap density are identified as the mechanisms responsible for Ge NMOS performance degradation. After eliminating the degradation mechanisms, the highest electron mobility in Ge NMOS to date, which is, to the best of our knowledge, ~1.5 times the universal Si mobility, is experimentally demonstrated for the Ge N-MOSFETs fabricated with ozone-oxidation surface passivation and low temperature S/D activation processes. View full abstract»

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  • Threshold Voltage Fluctuation by Random Telegraph Noise in Floating Gate nand Flash Memory String

    Page(s): 67 - 73
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    Read current fluctuation (ΔIread) due to random telegraph noise was measured from a cell in a NAND flash memory cell string, and its effect on threshold voltage fluctuation (ΔVth) was analyzed. Sixteen-level fluctuation (four traps) was observed in a 60-nm cell of a cell string (ΔIread/Iread of ~0.4). ΔIread increased with decreasing Lg, and ΔIread/Iread up to 0.75 was observed at 48 nm. ΔIread, ΔVth, and their relation were clearly analyzed with program/erase mode of a cell and pass cells in a string. Although ΔIread is largest when a read cell and pass cells are erased, ΔVth is largest when a read cell is erased and pass cells are programmed in a cell string. We also observed the specific noise amplitude under various conditions, such as the bit-line bias, the pass bias of unselected cells in the NAND strings, and the temperature. View full abstract»

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  • Germanium Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor Fabricated by Complementary-Metal–Oxide–Semiconductor-Compatible Process

    Page(s): 74 - 79
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB) |  | HTML iconHTML  

    This work presents a complementary metal-oxide-semiconductor-compatible top-down fabrication of Ge nanowires along with their integration into pMOSFETs with "HfO2/TaN" high-k/metal gate stacks. Lateral Ge wires down to 14 nm in diameter are achieved using a two-step dry etch process on a high-quality epitaxial Ge layer. To improve the interface quality between the Ge nanowire and the HfO2, thermally grown GeO2 and epitaxial-Si shells are used as interlayers. Devices with a GeO2 shell demonstrated excellent ION/IOFF ratios (>; 106), whereas the epitaxial-Si shell was found to improve the field-effect mobility of the holes in Ge nanowires to 254 cm2V-1 · s-1. View full abstract»

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  • Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor

    Page(s): 80 - 86
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    Low operating power is an important concern for sub-45-nm CMOS integrated circuits. Scaling of devices to below 45 nm leads to an increase in active power dissipation (CV2.f) and subthreshold power (IOFF.VDD)Hence, new device innovations are being explored to address these problems. In this paper, we simulate and experimentally investigate the source-pocket tunnel field-effect transistor (TFET), which is based on the principle of band-to-band tunneling, p-i-n and source-pocket TFETs are fabricated with different pocket conditions to observe the effect of the source-side pocket on device performance. Different annealing schemes (spike and conventional rapid thermal annealing) are used to study the effect of annealing conditions on TFET performance. The source-pocket TFET shows a higher ION (~10 times) and steeper subthreshold swing as compared to a p-i-n TFET. The ambipolar conduction is also reduced by using a low-doped drain extension. Low-temperature measurements of the source-pocket TFET were performed, and the subthreshold swing of the source-pocket TFET shows very little temperature dependence, which confirms the dominant source injection mechanism to be band-to-band tunneling. View full abstract»

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  • Performance of AlGaN/GaN High-Electron Mobility Transistors With AlSiN Passivation

    Page(s): 87 - 94
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    The performance of AlGaN/GaN high-electron mobility transistors that were passivated with AlSiN and SiN and fabricated side by side has been studied. It is found that the AlSiN passivation produced state-of-the-art devices, improving both small- and large-signal performance over the SiN passivation, particularly at higher drain bias. With large-signal excitation at 10 GHz, the effects of second-harmonic termination on the load pull were also studied. Significant improvements in the power-added efficiency were demonstrated. View full abstract»

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  • In situ Surface Passivation of Gallium Nitride for Metal–Organic Chemical Vapor Deposition of High-Permittivity Gate Dielectric

    Page(s): 95 - 102
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    We report the demonstration of novel techniques for surface passivation of gallium nitride (GaN), comprising the steps of in situ vacuum anneal (VA) and silane-ammonia (SiH4 + NH3) or silane (SiH4) treatment for GaN, prior to the formation of high-permittivity gate dielectric in a multichamber metal-organic chemical vapor deposition tool. The effects of VA temperature and the SiH4 + NH3 or SiH4 treatment temperature on interface quality was investigated. High-temperature capacitance-voltage characterization was also performed to probe the interface states near the midgap of GaN. Interface state density Dit as a function of energy was extracted. Without in situ passivation, a control TaN/HfAlO/GaN capacitor has a midgap Dit of ~2.0 × 1012 cm-2 · eV-1. This is reduced to ~4.0 × 1011 cm-2 · eV-1 and ~2.0 × 1010 cm-2 · eV-1 for samples that received the in situ SiH4 + NH3 treatment and in situ SiH4 treatment, respectively. View full abstract»

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  • Dark Current Mechanism in Bulk GaInNAs Lattice Matched to GaAs

    Page(s): 103 - 106
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    The reverse-bias current-voltage characteristics of a series of Ga1-xlnxNyAs1-y diodes with bandgap of between 0.87 and 1.04 eV are reported. At low bias, diffusion and generation-recombination currents are dominant at high and low temperatures, respectively. At high reverse bias, the dark current is insensitive to changes in temperature, which is indicative of tunneling current mechanisms. We also observe an exponential dependence of the dark current with the electric field in the mid-bias range for all our diodes, which may be explained by the Poole-Frenkel effect. View full abstract»

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  • Interface-Trap Effects in Inversion-Type Enhancement-Mode \hbox {InGaAs/ZrO}_{2} N-Channel MOSFETs

    Page(s): 107 - 114
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    Interface-trap effects are analyzed in inversion-type enhancement-mode In0.53Ga0.47/ZrO2 and In0.53Ga0.47As/In0.2Ga0.8As/ZrO2 n-channel MOSFETs by comparing the measurements and the numerical device simulations of dc transfer characteristics. Device simulations can reproduce measured threshold voltages under the hypothesis that interface traps are donorlike throughout the InGaAs band gap, allowing for strong inversion operation regardless of the relatively high interface-trap density. The effects induced by the donorlike interface traps in MOSFETs having a thin cap layer interposed between gate dielectric and channel are qualitatively different from those observed in standard MOSFETs (without the cap). Increasing the donorlike trap density decreases the threshold voltage in capped devices, whereas it leaves it unchanged in uncapped ones. As a result, donorlike interface traps can explain the threshold-voltage difference observed in MOSFETs with and without the cap. View full abstract»

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  • Doping Dependence of Thermal Oxidation on n-Type 4H-SiC

    Page(s): 115 - 121
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    The doping dependence of dry thermal oxidation rates in n-type 4H-SiC was investigated. The oxidation was performed in the temperature range of 1000 °C to 1200 °C for samples with nitrogen doping in the range of 6.5 × 1015 to 9.3 × 1018/cm3, showing a clear doping dependence. Samples with higher doping concentrations displayed higher oxidation rates. The results were interpreted using a modified Deal-Grove model. Linear and parabolic rate constants and activation energies were extracted. Increasing nitrogen led to an increase in the linear-rate-constant preexponential factor from 10-6 to 10-2 m/s and the parabolic-rate-constant preexponential factor from 10-9 to 10-6 m2/s. The increase in the linear rate constant was attributed to defects from doping-induced lattice mismatch, which tend to be more reactive than bulk crystal regions. The increase in the diffusion-limited parabolic rate constant was attributed to the degradation in the oxide quality originating from the doping-induced lattice mismatch. This degradation was confirmed by the observation of a decrease in the optical density of the grown oxide films from 1.4 to 1.24. The linear activation energy varied from 1.6 to 2.8 eV, while the parabolic activation energy varied from 2.7 to 3.3 eV, increasing with doping concentration. These increased activation energies were attributed to the higher nitrogen content, leading to an increase in the effective bond energy stemming from the difference in C-Si (2.82 eV) and Si-N (4.26 eV) binding energies. This paper provides crucial information in the engineering of SiO2 dielectrics for SiC metal-oxide-semiconductor structures, which typically involve regions of very different doping concentrations, and suggests that thermal oxidation at high doping concentrations in SiC may be defect mediated. View full abstract»

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  • Effect of Postdeposition Annealing in Oxygen Ambient on Gallium-Nitride-Based MOS Capacitors With Cerium Oxide Gate

    Page(s): 122 - 131
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    This paper presents the effects of postdeposition annealing temperatures (400, 600, 800, and 1000°C) in oxygen ambient on the metal-organic decomposed CeO2 films spin coated on an n-type GaN substrate. The compositions, structures, and morphologies of these samples are revealed by X-ray diffraction (XRD), field-emission scanning electron microscopy, and an atomic force microscope. XRD analysis discloses the presence of CeO2 films, α-Ce2O3, and an interfacial layer of β-Ga2O3. The formation of α-Ce2O3 is due to the phase transformation of CeO2, whereas the β-Ga2O3 interfacial layer is formed due to the inward diffusion of the released oxygen from CeO2 reacting with decomposed GaN. These characterization results are then correlated with the metal-oxide-semiconductor characteristics of the CeO2 gate annealed at different temperatures. It has been demonstrated that oxide annealed at 1000°C shows the lowest semiconductor-oxide interface-trap density, effective oxide charge, and the highest dielectric breakdown field. View full abstract»

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  • A Current-Transient Methodology for Trap Analysis for GaN High Electron Mobility Transistors

    Page(s): 132 - 140
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    Trapping is one of the most deleterious effects that limit performance and reliability in GaN HEMTs. In this paper, we present a methodology to study trapping characteristics in GaN HEMTs that is based on current-transient measurements. Its uniqueness is that it is amenable to integration with electrical stress experiments in long-term reliability studies. We present the details of the measurement and analysis procedures. With this method, we have investigated the trapping and detrapping dynamics of GaN HEMTs. In particular, we examined layer location, energy level, and trapping/detrapping time constants of dominant traps. We have identified several traps inside the AlGaN barrier layer or at the surface close to the gate edge and in the GaN buffer. View full abstract»

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  • Pseudo-CMOS: A Design Style for Low-Cost and Robust Flexible Electronics

    Page(s): 141 - 150
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    Thin-film transistors (TFTs) are a key element of flexible electronics implemented on low-cost substrates. Most TFT technologies, however, have only monotype-either n- or p-type-devices. In this paper, we propose a novel design style Pseudo-CMOS for flexible electronics that uses only monotype single-VT TFTs but has comparable performance with the complementary-type or dual-VT designs. The manufacturing cost and complexity can therefore be significantly reduced, whereas the circuit yield and reliability are enhanced with built-in postfabrication tunability. Digital cells are fabricated in two different TFT technologies, i.e., p-type self-assembled-monolayer-organic TFTs and n-type metal-oxide InGaZnO TFTs, to validate the proposed Pseudo-CMOS design style. To the best of our knowledge, this is the first design solution that has been experimentally proven to achieve superior performance for both types of TFT technologies. View full abstract»

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  • Printed WORM Memory on a Flexible Substrate Based on Rapid Electrical Sintering of Nanoparticles

    Page(s): 151 - 159
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    Fully printed low-voltage programmable resistive write-once-read-many (WORM) memory on a flexible substrate is investigated. The memory concept is demonstrated using inkjet-printed silver nanoparticle structures on a photopaper. The initial high-resistance state “0” is written into the low-resistance state “1” using rapid electrical sintering. A key advantage is low writing power and energy. The long-term stability of the initial nonsintered state is found to require special attention to obtain a sufficient shelf storage time. The memory design offers potential for high-throughput roll-to-roll production. View full abstract»

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  • Electrical Instability of the a-Si:H TFTs Fabricated by Maskless Laser-Write Lithography on a Spherical Surface

    Page(s): 160 - 164
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    We fabricated and characterized hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) with a channel length of 10 on both spherical and flat surfaces using maskless laser-write lithography (LWL). In addition to the electrical performance, the threshold voltage shift of the a-Si:H TFT under bias-temperature stress is investigated and discussed in comparison to a device fabricated on a flat surface. The obtained results show that the a-Si:H TFTs fabricated by LWL method on a curved surface are suitable for pixel switches and circuits, which are needed to realize image sensor arrays and/or displays on a nonplanar surface. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology