IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 1 • Jan. 2011

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  • Table of contents

    Publication Year: 2011, Page(s): C1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2011, Page(s): C2
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  • Editorial

    Publication Year: 2011, Page(s): 1
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  • List of Reviewers

    Publication Year: 2011, Page(s):2 - 7
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  • Floorplanning for Partially Reconfigurable FPGAs

    Publication Year: 2011, Page(s):8 - 17
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB) | HTML iconHTML

    Partial reconfiguration on heterogeneous field-programmable gate arrays with millions of gates yields better utilization of its different types of resources by swapping in and out the appropriate modules of one or more applications at any instant of time. Given a schedule of sub-task instances where each instance is specified as a netlist of active modules, reconfiguration overhead can be reduced ... View full abstract»

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  • Toward Automated ECOs in FPGAs

    Publication Year: 2011, Page(s):18 - 30
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (529 KB) | HTML iconHTML

    Engineering change orders (ECOs), which are used to apply late-stage specification changes and bug fixes, have become an important part of the field-programmable gate array design flow. ECOs are beneficial since they are applied directly to a placed-and-routed netlist which preserves most of the engineering effort invested previously. Unfortunately, designers often apply ECOs in a manual fashion w... View full abstract»

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  • Determining the Number of Paths in Decision Diagrams by Using Autocorrelation Coefficients

    Publication Year: 2011, Page(s):31 - 44
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB) | HTML iconHTML

    This paper deals with the number of paths in multiterminal binary decision diagrams (MTBDDs) and shared binary decision diagrams (SBDDs) representing a set of Boolean functions. It is shown that the number of paths in an MTBDD (SBDD) can be uniquely determined by values of specific weighted-autocorrelation coefficients. An analytical expression for the number of paths as a linear function of the v... View full abstract»

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  • Hierarchical Multialgorithm Parallel Circuit Simulation

    Publication Year: 2011, Page(s):45 - 58
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (814 KB) | HTML iconHTML

    The emergence of multicore and many-core processors has introduced new opportunities and challenges to electronic design automation research and development. While the availability of increasing parallel computing power holds new promise to address many challenges in computer-aided design (CAD), the leverage of hardware parallelism can only be possible with a new generation of parallel CAD applica... View full abstract»

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  • Bound-Based Statistically-Critical Path Extraction Under Process Variations

    Publication Year: 2011, Page(s):59 - 71
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (271 KB) | HTML iconHTML

    This paper introduces a bound-based approach to extract a pre-specified number of statistically-critical paths under process variations. These are the paths with the highest “violation probability,” which indicates the probability that a path would violate a given timing constraint. Our approach requires pre-computation of the violation probability of all the nodes and edges in the c... View full abstract»

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  • GRIP: Global Routing via Integer Programming

    Publication Year: 2011, Page(s):72 - 84
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB) | HTML iconHTML

    This paper introduces GRIP, a global routing technique via integer programming. GRIP optimizes wirelength and via cost directly without going through a traditional layer assignment phase. Candidate routes spanning all the metal layers are generated using a linear programming pricing phase that formally accounts for the impact of existing candidate routes when generating new ones. To make an intege... View full abstract»

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  • Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints

    Publication Year: 2011, Page(s):85 - 95
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (787 KB) | HTML iconHTML

    In today's system-on-chip designs, both digital and analog parts of a circuit will be implemented on the same chip. Parasitic mismatch induced by layout will affect circuit performance significantly for analog designs. Consideration of symmetry and common centroid constraints during placement can help to reduce these errors. Besides these two specific types of placement constraints, other constrai... View full abstract»

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  • Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization

    Publication Year: 2011, Page(s):96 - 109
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1166 KB) | HTML iconHTML

    In synchronous systems, clock tree causes high peak current at clock edges, increasing power/ground noise significantly, if the clock tree is not carefully designed. This paper addresses the problem of minimizing power/ground noise in the clock tree synthesis. Contrary to the previous approaches which only make use of assigning polarities to clock buffers to reduce power/ground noise, our approach... View full abstract»

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  • Program Phase-Aware Dynamic Voltage Scaling Under Variable Computational Workload and Memory Stall Environment

    Publication Year: 2011, Page(s):110 - 123
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB) | HTML iconHTML

    Most complex software programs are characterized by program phase behavior and runtime distribution. Dynamism of the two characteristics often makes the design-time workload prediction difficult and inefficient. Especially, memory stall time whose variation is significant in memory-bound applications has been mostly neglected or handled in a too simplistic manner in previous works. In this paper, ... View full abstract»

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  • Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip

    Publication Year: 2011, Page(s):124 - 134
    Cited by:  Papers (37)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1213 KB) | HTML iconHTML

    Through silicon vias (TSVs) provide an efficient way to support vertical communication among different layers of a vertically stacked chip, enabling scalable 3-D networks-on-chip (NoC) architectures. Unfortunately, low TSV yields significantly impact the feasibility of high-bandwidth vertical connectivity. In this paper, we present a semi-automated design flow for 3-D NoCs including a defect-toler... View full abstract»

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  • Cost-Effective Power-Aware Core Testing in NoCs Based on a New Unicast-Based Multicast Scheme

    Publication Year: 2011, Page(s):135 - 147
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (925 KB) | HTML iconHTML

    Reuse of network-on-chip (NoC) for test data and test response delivery is attractive. However, previous techniques do not effectively use the bandwidths of the network by delivering test packets to all cores separately, which can make very much test cost and test data volume. The NoC core testing problem is formulated as a unicast-based multicast problem in order to reduce test data delivery time... View full abstract»

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  • Reducing Test Execution Cost of Integrated, Heterogeneous Systems Using Continuous Test Data

    Publication Year: 2011, Page(s):148 - 158
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB) | HTML iconHTML

    Integrated, heterogeneous systems are comprehensively tested to verify whether their performance specifications fall within some acceptable ranges. However, explicitly testing every manufactured instance against all of its specifications can be expensive due to the complex requirements for test setup, stimulus application, and response measurement. To reduce manufacturing test cost, we have develo... View full abstract»

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  • On Efficient LHS-Based Yield Analysis of Analog Circuits

    Publication Year: 2011, Page(s):159 - 163
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (230 KB) | HTML iconHTML

    The Latin hypercube sampling (LHS) has been used as a variance-reduction estimation tool for an efficient sampling-based variability analysis of analog circuits. For a certain estimation confidence interval, a lower number of LHS samples is needed than that of Monte Carlo due to the estimation variance reduction. In this paper, an analysis of variance decomposition of the indicator function, the y... View full abstract»

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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2011, Page(s): 164
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2011, Page(s): C3
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  • Blank page [back cover]

    Publication Year: 2011, Page(s): C4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu