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IEEE Transactions on Circuits and Systems II: Express Briefs

Issue 12 • Date Dec. 2010

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Displaying Results 1 - 24 of 24
  • Table of contents

    Publication Year: 2010, Page(s):C1 - 1
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Publication Year: 2010, Page(s): C2
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  • A Multiphase Multipath Technique With Digital Phase Shifters for Harmonic Distortion Cancellation

    Publication Year: 2010, Page(s):921 - 925
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (175 KB) | HTML iconHTML

    Nonlinearities in transmitter circuits, such as power amplifiers, cause degradation in system performance and adjacent-channel spectral growth interference. Polyphase multipath is considered among the techniques that can compensate the nonlinearities, creating a clean output spectrum. However, the polyphase technique requires analog phase shifters that consume considerable power. Aiming at reducin... View full abstract»

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  • A 10-Gb/s Inductorless Transimpedance Amplifier

    Publication Year: 2010, Page(s):926 - 930
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (666 KB) | HTML iconHTML

    A new technique to design an inductorless transimpedance amplifier (TIA) is introduced. This technique uses N similar TIAs in parallel configuration to boost the overall bandwidth while keeping the transimpedance gain constant. Using this method, we design and implement a 10-Gb/s inductorless TIA with an active area of only 0.06 mm2 and a differential transimpedance gain of 62 dB... View full abstract»

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  • Effect of Reference Clock Jitter and Demonstration of Near Image-Free Operation for the ADPLL

    Publication Year: 2010, Page(s):931 - 935
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (139 KB) | HTML iconHTML

    The effect of reference clock jitter on the all-digital phase-locked loop (ADPLL) is considered. The analog-to-digital interface [e.g., a time-to-digital converter (TDC)] is considered only briefly. For the digital-to-analog interface [e.g., a digitally controlled oscillator (DCO)], the analysis is studied in detail. The power spectral density and the integrated power of the ADPLL's output phase n... View full abstract»

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  • Phase Frequency Detector With Minimal Blind Zone for Fast Frequency Acquisition

    Publication Year: 2010, Page(s):936 - 940
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (479 KB) | HTML iconHTML

    Blind zone in a phase-frequency detector (PFD) reduces the input detection range and aggravates cycle slips. This brief analyzes the blind zone in latch-based PFDs and proposes a technique that removes the blind zone caused by the precharge time of the internal nodes. With the proposed technique, the PFD achieves a small blind zone close to the limit imposed by process-voltage-temperature variatio... View full abstract»

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  • Binary Phase Detector Gain in Bang-Bang Phase-Locked Loops With DCO Jitter

    Publication Year: 2010, Page(s):941 - 945
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (186 KB) | HTML iconHTML

    Bang-bang phase-locked loops are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). In the presence of jitter, the nonlinear loop is typically analyzed by linearizing the BPD and applying linear transfer functions in the analysis. In contrast to a linear phase detector, the linearized gain of a BPD depends on the rms jitter and the type of jitter (either ... View full abstract»

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  • A Programmable Edge-Combining DLL With a Current-Splitting Charge Pump for Spur Suppression

    Publication Year: 2010, Page(s):946 - 950
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (915 KB) | HTML iconHTML

    A programmable edge-combining delay-locked loop (DLL) with fast switching transient and reduced output spur is presented in this work. With 12 delay cells adopted in the DLL, the programmable frequency-multiplied output can be quickly switched between ×6, ×3, and ×2 without affecting the lock state of the DLL. Output spur is suppressed by reducing the DLL phase offset in the l... View full abstract»

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  • A Sub-10- \mu\hbox {W} Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications

    Publication Year: 2010, Page(s):951 - 955
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB) | HTML iconHTML

    This brief presents an all digitally controlled oscillator (DCO) design with two newly proposed hysteresis delay cells (HDCs) for wireless body area network applications. According to circuit topologies, the two HDCs are defined as on-off and cascaded HDCs that provide various propagation delay values. These HDCs form a simple oscillator structure based on a power-of-2 delay stage DCO (P2-DCO) arc... View full abstract»

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  • A Frequency Model of a Continuously Driven Clocked CMOS Comparator

    Publication Year: 2010, Page(s):956 - 960
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (346 KB) | HTML iconHTML

    A frequency model of a continuously driven clocked CMOS comparator with the effect of the input signal during regeneration is presented. The model utilizes a small-signal linear model derived from the theoretical analysis of the comparison error caused by the transition from the tracking mode to the regeneration mode. The comparison error voltage is a function of input signal frequency and is repr... View full abstract»

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  • An Offset Double Conversion Technique for Digital Calibration of Pipelined ADCs

    Publication Year: 2010, Page(s):961 - 965
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (390 KB) | HTML iconHTML

    An offset double conversion technique to calibrate pipelined analog-to-digital converters (ADCs) is presented, in which self-equalization is performed using one ADC, resulting in fast convergence for high-resolution applications. The approach also promises significant improvement of signal-to-noise-plus-distortion ratio (SNDR), simultaneous multistage calibration, and minimal analog circuit modifi... View full abstract»

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  • A New DAC Mismatch Shaping Technique for Sigma–Delta Modulators

    Publication Year: 2010, Page(s):966 - 970
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (179 KB) | HTML iconHTML

    A new ΣΔ modulator architecture that shapes digital-to-analog converter (DAC) mismatches in a manner similar to quantization noise shaping is proposed, allowing operation with low oversampling ratios, high-resolution quantizers, and compact logic. It is shown that the proposed architecture entails a smaller feedback logic delay than data-weighted-averaging techniques, providing a fou... View full abstract»

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  • Direct Synthesis of Parallel-Connected Symmetrical Two-Port Filters

    Publication Year: 2010, Page(s):971 - 974
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (367 KB) | HTML iconHTML

    This brief presents a general technique for the synthesis of parallel-connected two-port networks. This is based on the even- and odd-mode admittances of a standard Chebyshev network. The expressions for the even/odd-mode admittance are used to synthesize the low-pass network into branches of subnetworks connected in parallel between the source and the load. These together will have the same chara... View full abstract»

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  • Fractional-Order Memristor-Based Chua's Circuit

    Publication Year: 2010, Page(s):975 - 979
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (251 KB) | HTML iconHTML

    This express brief deals with the memristor-based Chua's circuit. For the first time, the fractional-order model for such system is presented. A numerical solution of the fractional-order memristor-based Chua's equations is derived for simulations. The dynamical behavior and stability analysis of this system are described and investigated as well. View full abstract»

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  • A 0.45-V 300-MHz 10T Flowthrough SRAM With Expanded write/ read Stability and Speed-Area-Wise Array for Sub-0.5-V Chips

    Publication Year: 2010, Page(s):980 - 985
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (944 KB) | HTML iconHTML

    Capable of only solving the read-stability issue, many 8T-10T static RAM (SRAM) cells require extra write-assist circuits to achieve low supply voltage operation. This brief proposes a novel 10T SRAM cell and a hybrid-divided-block array to enhance the read-and-write stability while achieving a higher operating speed with a smaller area overhead for sub-0.5 V applications. A 16-Kb 128-row 10T flow... View full abstract»

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  • Data-Dependent Statistical Memory Model for Passive Array of Memristive Devices

    Publication Year: 2010, Page(s):986 - 990
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (411 KB) | HTML iconHTML

    A 2 × 2 equivalent statistical circuit model is presented to deal with sneak currents and random data distributions for n × m passive memory arrays of memristive devices. The data-dependent 2 × 2 circuit model enables a broad range of analysis, such as the optimum detection voltage margin, with computational efficiency and has no limit on the memory array size. I... View full abstract»

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  • Fingerprint Image Processing Acceleration Through Run-Time Reconfigurable Hardware

    Publication Year: 2010, Page(s):991 - 995
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (689 KB) | HTML iconHTML

    To the best of the authors' knowledge, this is the first brief that implements a complete automatic fingerprint-based authentication system (AFAS) application under a dynamically partial self-reconfigurable field-programmable gate array (FPGA). The main benefits of this implementation are the acceleration of the processing reached by the parallelism inherent to the hardware design, the high level ... View full abstract»

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  • Randomness Enhancement Using Digitalized Modified Logistic Map

    Publication Year: 2010, Page(s):996 - 1000
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    In this brief, a nonlinear digitalized modified logistic map-based pseudorandom number generator (DMLM-PRNG) is proposed for randomness enhancement. Two techniques, i.e., constant parameter selection and output sequence scrambling, are employed to reduce the computation cost without sacrificing the complexity of the output sequence. Statistical test results show that with only one multiplication, ... View full abstract»

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  • M -DCSK-Based Chaotic Communications in MIMO Multipath Channels With No Channel State Information

    Publication Year: 2010, Page(s):1001 - 1005
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (425 KB) | HTML iconHTML

    We consider chaotic digital communications in multiple-input-multiple-output (MIMO) wireless multipath fading channels. In particular, we focus on systems that employ M -ary differential chaos shift keying (M-DCSK). We consider two transceiver schemes, both of which require no channel state information at either the transmitter or the receiver. The first one employs a distinct chaoti... View full abstract»

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  • Why we joined ... [advertisement]

    Publication Year: 2010, Page(s): 1006
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  • 2011 IEEE membership form

    Publication Year: 2010, Page(s):1007 - 1008
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  • 2010 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 57

    Publication Year: 2010, Page(s):1009 - 1032
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2010, Page(s): C3
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

    Publication Year: 2010, Page(s): C4
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Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org