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Computers and Digital Techniques, IEE Proceedings E

Issue 3 • Date May 1993

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Displaying Results 1 - 5 of 5
  • Modular architecture for high performance implementation of 2-dimensional fast Fourier transform

    Publication Year: 1993 , Page(s): 167 - 173
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (380 KB)  

    The paper proposes new structural schemes of high-throughput processors executing 2-dimensional fast Fourier transforms (FFTs) by the column-row method and the vector-radix algorithm. These structures offer a simplified system of data commutation (eliminating cross-commutations of complex data flows), and a simple ordering of input array without preliminary accumulation. These structures also eliminate overlap of input arrays and matrix-transposition devices during computation. View full abstract»

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  • Methodology for efficiently inserting and condensing test points (CMOS ICs testing)

    Publication Year: 1993 , Page(s): 154 - 160
    Cited by:  Papers (8)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (476 KB)  

    A technique for eliminating hard-to-test or untestable nodes in CMOS integrated circuits is presented. The technique is characterised by a speed degradation smaller than that introduced by others. Also, efficient methods for inserting and condensing test points in combinational circuits are introduced. The experimental results show that only few test points are needed to dramatically reduce the number of random patterns which are required to achieve very close to 100% fault coverage. View full abstract»

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  • Enhancing testability of VLSI arrays for fast Fourier transform

    Publication Year: 1993 , Page(s): 161 - 166
    Cited by:  Papers (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (356 KB)  

    Fast-Fourier-transform (FFT) algorithms are used in various digital signal-processing applications such as linear filtering, correlation analysis and spectrum analysis. With the advent of very large-scale-integration (VLSI) technology, a large collection of processing elements can be gathered to achieve high-speed computation economically. However, owing to the low pin-count/component-count ratio, the controllability and observability of such circuits decrease significantly. As a result, testing of such highly complex and dense circuits becomes very difficult and expensive. M-testability conditions for butterfly-connected and shuffle-connected FFT arrays are proposed. Based on them, a novel design-for-testability approach is presented and applied to the module-level systolic FFT arrays. The M-testability conditions guarantee 100% single-module-fault testability with a minimum number of test patterns. View full abstract»

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  • Self-testing approaches for VLSI arrays

    Publication Year: 1993 , Page(s): 175 - 183
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (608 KB)  

    A self-testing method which is applicable 1- and 2-dimensional arrays, is presented. The method is based on a state-table-verification approach and a criterion referred to as GI (group identical) testability. GI testability is an extension and modification of PI (partition identical) testability and it is used to simplify response verification for self-testing. It is shown that the response verifier for PI testability does not always detect all faults and a new response verifier for GI-testable arrays is proposed. CGI-testable arrays which are simultaneously C and GI testable, are analysed. It is proved that a C-testable 1-dimensional array with n cells is GI testable if n>or=2T, where T is the least common multiple of the test sequences for verifying a cell in the array. Design for testability approaches for unilateral and bilateral arrays are proposed, and similar conditions are developed for 2-dimensional arrays. Methods for reducing the size of CGI-testable unilateral and bilateral arrays are discussed. View full abstract»

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  • Optimal tile partition for space region of integrated circuits geometry

    Publication Year: 1993 , Page(s): 145 - 153
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (548 KB)  

    An optimal tile partition (OTP) is presented for partitioning the space region of a VLSI layout plane into rectangular space tiles. It modifies the corner stitching data structure to optimise the space tile partition. There is a serious restriction in the original corner stitching data structure, i.e. the solid rectangles cannot overlap each other, whereas the authors OTP allows overlapping. This paper also shows three theorems with rigorous proofs and experimental results to obtain the minimal number of the space tiles through the OTP. Moreover, a dynamic plane-sweep algorithm based on region query for the OTP has been developed. Using the OTP, the memory efficiency and the local query operations of the original corner stitching data structure have been enhanced. View full abstract»

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