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IEE Proceedings E - Computers and Digital Techniques

Issue 3 • May 1993

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  • Self-testing approaches for VLSI arrays

    Publication Year: 1993, Page(s):175 - 183
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (608 KB)

    A self-testing method which is applicable 1- and 2-dimensional arrays, is presented. The method is based on a state-table-verification approach and a criterion referred to as GI (group identical) testability. GI testability is an extension and modification of PI (partition identical) testability and it is used to simplify response verification for self-testing. It is shown that the response verifi... View full abstract»

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  • Modular architecture for high performance implementation of 2-dimensional fast Fourier transform

    Publication Year: 1993, Page(s):167 - 173
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (380 KB)

    The paper proposes new structural schemes of high-throughput processors executing 2-dimensional fast Fourier transforms (FFTs) by the column-row method and the vector-radix algorithm. These structures offer a simplified system of data commutation (eliminating cross-commutations of complex data flows), and a simple ordering of input array without preliminary accumulation. These structures also elim... View full abstract»

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  • Optimal tile partition for space region of integrated circuits geometry

    Publication Year: 1993, Page(s):145 - 153
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (548 KB)

    An optimal tile partition (OTP) is presented for partitioning the space region of a VLSI layout plane into rectangular space tiles. It modifies the corner stitching data structure to optimise the space tile partition. There is a serious restriction in the original corner stitching data structure, i.e. the solid rectangles cannot overlap each other, whereas the authors OTP allows overlapping. This ... View full abstract»

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  • Methodology for efficiently inserting and condensing test points (CMOS ICs testing)

    Publication Year: 1993, Page(s):154 - 160
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (476 KB)

    A technique for eliminating hard-to-test or untestable nodes in CMOS integrated circuits is presented. The technique is characterised by a speed degradation smaller than that introduced by others. Also, efficient methods for inserting and condensing test points in combinational circuits are introduced. The experimental results show that only few test points are needed to dramatically reduce the nu... View full abstract»

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  • Enhancing testability of VLSI arrays for fast Fourier transform

    Publication Year: 1993, Page(s):161 - 166
    Cited by:  Papers (11)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (356 KB)

    Fast-Fourier-transform (FFT) algorithms are used in various digital signal-processing applications such as linear filtering, correlation analysis and spectrum analysis. With the advent of very large-scale-integration (VLSI) technology, a large collection of processing elements can be gathered to achieve high-speed computation economically. However, owing to the low pin-count/component-count ratio,... View full abstract»

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