IEEE Transactions on Computers

Issue 1 • Jan. 2011

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  • [Front cover]

    Publication Year: 2011, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2011, Page(s): c2
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  • Editorial

    Publication Year: 2011, Page(s): 1
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  • State of the Journal

    Publication Year: 2011, Page(s): 2
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  • SPECIAL SECTION ON DEPENDABLE COMPUTER ARCHITECTURE 
  • Guest Editors' Introduction: Special Section on Dependable Computer Architecture

    Publication Year: 2011, Page(s):3 - 4
    Cited by:  Papers (1)
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  • StageNet: A Reconfigurable Fabric for Constructing Dependable CMPs

    Publication Year: 2011, Page(s):5 - 19
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2030 KB) | HTML iconHTML

    CMOS scaling has long been a source of dramatic performance gains. However, semiconductor feature size reduction has resulted in increasing levels of operating temperatures and current densities. Given that most wearout mechanisms are highly dependent on these parameters, significantly higher failure rates are projected for future technology generations. Consequently, fault tolerance, which has tr... View full abstract»

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  • Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache

    Publication Year: 2011, Page(s):20 - 34
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2030 KB) | HTML iconHTML

    With increasing parameter variations in nanometer technologies, on-chip cache in processor is becoming highly vulnerable to runtime failures induced by “soft error,” voltage, or thermal noise and aging effects. Nondeterministic and unreliable memory operation due to these runtime failures can be addressed by: 1) designing the memory for worst-case scenarios and/or 2) runtime error de... View full abstract»

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  • Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines

    Publication Year: 2011, Page(s):35 - 49
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2104 KB) | HTML iconHTML

    Aggressive technology scaling to 45 nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-chip caches, it is important to protect these SRAM structures against lifetime and manufacture-time failures. Designers typically overprovision caches with additional resources to overcome hard faults. However, static allo... View full abstract»

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  • Adaptive Cache Design to Enable Reliable Low-Voltage Operation

    Publication Year: 2011, Page(s):50 - 63
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1562 KB) | HTML iconHTML

    The performance/energy trade-off is widely acknowledged as a primary design consideration for modern processors. A less discussed, though equally important, trade-off is the reliability/energy trade-off. Many design features that increase reliability (e.g., redundancy, error detection, and correction) have the side effect of consuming more energy. Many energy-saving features (e.g., voltage scaling... View full abstract»

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  • Improving Availability of RAID-Structured Storage Systems by Workload Outsourcing

    Publication Year: 2011, Page(s):64 - 79
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1183 KB) | HTML iconHTML

    Due to the contention for the shared disk bandwidth, the user I/O intensity can significantly impact the performance of the online low-priority background tasks, thus reducing the reliability and availability of RAID-structured storage systems. In this paper, we propose a novel and practical scheme, called WorkOut (I/O Workload Outsourcing), to significantly boost the performance of those low-prio... View full abstract»

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  • Flash-Aware RAID Techniques for Dependable and High-Performance Flash Memory SSD

    Publication Year: 2011, Page(s):80 - 92
    Cited by:  Papers (56)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1727 KB) | HTML iconHTML

    Solid-state disks (SSDs), which are composed of multiple NAND flash chips, are replacing hard disk drives (HDDs) in the mass storage market. The performances of SSDs are increasing due to the exploitation of parallel I/O architectures. However, reliability remains as a critical issue when designing a large-scale flash storage. For both high performance and reliability, Redundant Arrays of Inexpens... View full abstract»

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  • An Architecture for Fault-Tolerant Computation with Stochastic Logic

    Publication Year: 2011, Page(s):93 - 105
    Cited by:  Papers (117)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2167 KB) | HTML iconHTML

    Mounting concerns over variability, defects, and noise motivate a new approach for digital circuitry: stochastic logic, that is to say, logic that operates on probabilistic signals and so can cope with errors and uncertainty. Techniques for probabilistic analysis of circuits and systems are well established. We advocate a strategy for synthesis. In prior work, we described a methodology for synthe... View full abstract»

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  • XHive: Efficient Cooperative Caching for Virtual Machines

    Publication Year: 2011, Page(s):106 - 119
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1972 KB) | HTML iconHTML

    Since a virtual machine independently uses its own caching policy, redundant disk operations exacerbate the I/O virtualization overhead when virtual machines access large amounts of data on shared storage. This paper presents XHive, an efficient cooperative caching system that is implemented at the virtualization layer, for consolidated environments. Our proposed scheme globally manages buffer cac... View full abstract»

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  • Speed Up Statistical Spam Filter by Approximation

    Publication Year: 2011, Page(s):120 - 134
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (3710 KB) | HTML iconHTML

    Statistical-based Bayesian filters have become a popular and important defense against spam. However, despite their effectiveness, their greater processing overhead can prevent them from scaling well for enterprise level mail servers. For example, the dictionary lookups that are characteristic of this approach are limited by the memory access rate, therefore relatively insensitive to increases in ... View full abstract»

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  • Packed AES-GCM Algorithm Suitable for AES/PCLMULQDQ Instructions

    Publication Year: 2011, Page(s):135 - 138
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1179 KB) | HTML iconHTML

    The level of interest in Galois Counter Mode (GCM) Authenticated Encryption rose significantly within the last few years. GCM is interesting because it is the only authenticated encryption standard that can be implemented in a fully pipelined or parallelized way and it is the most appropriate for encrypting packetized data. McGrew and Viega [CHECK END OF SENTENCE] described (but did not detail) ho... View full abstract»

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  • 2010 Annual Reviewers List

    Publication Year: 2011, Page(s):139 - 143
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  • Distinguish yourself with the CSDP [advertisement]

    Publication Year: 2011, Page(s): 144
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  • 2010 Annual Index

    Publication Year: 2011, Page(s): Online Only
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  • TC Information for authors

    Publication Year: 2011, Page(s): c3
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  • [Back cover]

    Publication Year: 2011, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org