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IEEE Computer Architecture Letters

Issue 2 • Feb. 2010

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Displaying Results 1 - 18 of 18
  • [Front cover]

    Publication Year: 2010, Page(s): c1
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  • Editorial Board [Cover2]

    Publication Year: 2010, Page(s): c2
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  • Editorial: Letter from the Editor-in-Chief

    Publication Year: 2010, Page(s):37 - 44
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  • ParMiBench - An Open-Source Benchmark for Embedded Multiprocessor Systems

    Publication Year: 2010, Page(s):45 - 48
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (158 KB) | HTML iconHTML

    Multicore processors are the main computing platform in laptops, desktop, and servers today, and are making their way into the embedded systems market also. Using benchmarks is a common approach to evaluate the performance of a system. However, benchmarks for embedded systems have so far been either targeted for a uni-processor environment, e.g., MiBench,or have been commercial, e.g., MultiBench b... View full abstract»

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  • Boomerang: Reducing Power Consumption of Response Packets in NoCs with Minimal Performance Impact

    Publication Year: 2010, Page(s):49 - 52
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (342 KB) | HTML iconHTML

    Most power reduction mechanisms for NoC channel buffers rely on on-demand wakeup to transition from a low-power state to the active state. Two drawbacks of on-demand wakeup limit its effectiveness: 1) performance impact caused by wakeup delays, and 2) energy and area cost of sleep circuitry itself. What makes the problem harder to solve is that solutions to either problem tend to exacerbate the ot... View full abstract»

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  • The Accelerator Store framework for high-performance, low-power accelerator-based systems

    Publication Year: 2010, Page(s):53 - 56
    Cited by:  Papers (11)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (173 KB) | HTML iconHTML

    Hardware acceleration can increase performance and reduce energy consumption. To maximize these benefits, accelerator- based systems that emphasize computation on accelerators (rather than on general purpose cores) should be used. We introduce the “accelerator store,” a structure for sharing memory between accelerators in these accelerator-based systems. The accelerator store simplif... View full abstract»

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  • Centralized Adaptive Routing for NoCs

    Publication Year: 2010, Page(s):57 - 60
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (493 KB) | HTML iconHTML

    As the number of applications and programmable units in CMPs and MPSoCs increases, the Network-on-Chip (NoC) encounters diverse and time dependent traffic loads. This trend motivates the introduction of NoC load-balanced, adaptive routing mechanisms that achieve higher throughput as compared with traditional oblivious routing schemes that are perceived better suited for hardware implementations. H... View full abstract»

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  • Fractal Consistency: Architecting the Memory System to Facilitate Verification

    Publication Year: 2010, Page(s):61 - 64
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB) | HTML iconHTML

    One of the most challenging problems in developing a multicore processor is verifying that the design is correct, and one of the most difficult aspects of pre-silicon verification is verifying that the memory system obeys the architecture's specified memory consistency model. To simplify the process of pre-silicon design verification, we propose a system model called the Fractally Consistent Model... View full abstract»

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  • Advertisement - IEEE Transactions on Computers Celebrates 60 Years

    Publication Year: 2010, Page(s): 65
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  • 2011 IEEE Computer Society Simulator Design Competition

    Publication Year: 2010, Page(s): 66
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  • Advertisement - Special Student Offer

    Publication Year: 2010, Page(s): 67
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  • Advertisement - Distinguish Yourself With the CSDP

    Publication Year: 2010, Page(s): 68
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  • Conference Proceedings Services (CPS) [advertisement]

    Publication Year: 2010, Page(s): 69
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  • IEEE Computer Society Jobs

    Publication Year: 2010, Page(s): 70
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  • Advertisement - Stay Connected to the IEEE Computer Society

    Publication Year: 2010, Page(s): 71
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  • Advertisement - Computer Society Digital Library

    Publication Year: 2010, Page(s): 72
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  • Information for authors

    Publication Year: 2010, Page(s): c3
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  • IEEE Computer Society [Cover4]

    Publication Year: 2010, Page(s): c4
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Aims & Scope

IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. 

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Meet Our Editors

Editor-in-Chief
Daniel J. Sorin
Duke University
Electrical & Computer Engineering
PO Box 90291
Durham, NC 27708
e-mail: sorin@ee.duke.edu