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IEEE Design & Test of Computers

Issue 5 • Date Sept.-Oct. 2010

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  • [Front cover]

    Publication Year: 2010, Page(s): c1
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  • [Front cover]

    Publication Year: 2010, Page(s): c2
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  • Call for Papers

    Publication Year: 2010, Page(s): 1
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  • Toc 
  • Table of Contents

    Publication Year: 2010, Page(s): 2
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  • Next-generation design and test innovations

    Publication Year: 2010, Page(s): 4
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  • [Masthead]

    Publication Year: 2010, Page(s): 5
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  • Measurement-Based Ring Oscillator Variation Analysis

    Publication Year: 2010, Page(s):6 - 13
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (525 KB) | HTML iconHTML

    As transistor size scales down, unavoidable process variations are rapidly increasing. Consequently, it's essential for designers to accurately estimate within-die and interdie variations so that circuits and integrated systems can operate correctly. This article describes an analysis of ring oscillators that were designed in 180-nm and 100-nm CMOS technologies, and discusses the oscillators' freq... View full abstract»

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  • Speeding Up Physical Synthesis with Transactional Timing Analysis

    Publication Year: 2010, Page(s):14 - 25
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (555 KB) | HTML iconHTML

    Modern physical-synthesis flows operate on very large designs and perform increasingly aggressive timing optimizations. Traditional incremental timing analysis now represents the single greatest bottleneck in such optimizations and lacks the features necessary to support them efficiently. This article describes a paradigm of transactional timing analysis, which, together with incremental updates, ... View full abstract»

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  • Dynamic Task Mapping for MPSoCs

    Publication Year: 2010, Page(s):26 - 35
    Cited by:  Papers (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB) | HTML iconHTML

    Multiprocessor-system-on-a-chip (MPSoC) applications can consist of a varying number of simultaneous tasks and can change even after system design, enforcing a scenario that requires the use of dynamic task mapping. This article investigates dynamic task-mapping heuristics targeting reduction of network congestion in network-on-chip (NoC)-based MPSoCs. The proposed heuristics achieve up to 31% sma... View full abstract»

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  • A Common Language Framework for Next-Generation Embedded Testing

    Publication Year: 2010, Page(s):36 - 49
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (454 KB) | HTML iconHTML

    This article describes the New Scan Description Language (NSDL), which can efficiently describe embedded-testing resources for automated test generation. The authors evaluate NSDL in the context of the proposed IEEE P1687 standard. They conduct a theoretical analysis for each requirement of this standard and identify the NSDL code solution for each point. They also explain how NSDL naturally fits ... View full abstract»

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  • BIST to Detect and Characterize Transient and Parametric Failures

    Publication Year: 2010, Page(s):50 - 59
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB) | HTML iconHTML

    The continual scaling of device dimensions is increasing both parametric failures, stemming from circuit marginality issues, and soft errors, from the impact of high-energy particles on semiconductor surfaces. Effectively detecting and estimating such intermittent failures is crucial for reliability, availability, and serviceability (RAS) characterization of chips. This BIST-based approach disting... View full abstract»

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  • Designing Chips without Guarantees

    Publication Year: 2010, Page(s):60 - 67
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB) | HTML iconHTML

    This roundtable is based on the 2010 Design Automation Conference session "Computing without Guarantees," which looked at how nondeterministic computing might be the wave of the future. The process of electronic system design has traditionally conformed to an axiom: the specification and implementation must be equivalent in a numerical or Boolean sense. But a wide range of application domains, inc... View full abstract»

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  • Spray-painting on the wall of EDA [review of EDAgraffiti (McLellan, P.; 2010)]

    Publication Year: 2010, Page(s):68 - 69
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  • CEDA Currents

    Publication Year: 2010, Page(s):70 - 71
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  • Conference Reports

    Publication Year: 2010, Page(s):72 - 73
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  • Design Automation Technical Committee Newsletter

    Publication Year: 2010, Page(s):74 - 77
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  • Test Technology TC Newsletter

    Publication Year: 2010, Page(s):78 - 79
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  • The ABCs of ITC

    Publication Year: 2010, Page(s): 80
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (103 KB) | HTML iconHTML

    This year's ITC, to be held 31 October–5 November in Austin, Texas, will explore the frontiers of test, through advanced research topics and case studies. Additionally, a basic tutorial will cover the fundamentals of test. Panel discussions will focus on why some analog test technologies are taking so long to be adopted, and will provide methods for chip bring-up. An Advanced Industrial... View full abstract»

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  • [Advertisement - Back cover]

    Publication Year: 2010, Page(s): c3
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  • [Advertisement - Back cover]

    Publication Year: 2010, Page(s): c4
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty