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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 11 • Date Nov. 2010

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Displaying Results 1 - 24 of 24
  • Table of contents

    Publication Year: 2010 , Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2010 , Page(s): C2
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  • Stochastic Flash Analog-to-Digital Conversion

    Publication Year: 2010 , Page(s): 2825 - 2833
    Cited by:  Papers (12)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1361 KB) |  | HTML iconHTML  

    A stochastic flash analog-to-digital converter (ADC) is presented. A standard flash uses a resistor string to set individual comparator trip points. A stochastic flash ADC uses random comparator offset to set the trip points. Since the comparators are no longer sized for small offset, they can be shrunk down into digital cells. Using comparators that are implemented as digital cells produces a large variation of comparator offset. Typically, this is considered a disadvantage, but in our case, this large standard deviation of offset is used to set the input signal range. By designing an ADC that is made up entirely of digital cells, it is a natural candidate for a synthesizable ADC. Comparator trip points follow the nonlinear transfer function described by a Gaussian cumulative distribution function, and a technique is presented that reduces this nonlinearity by changing the overall transfer function of the stochastic flash ADC. A test chip is fabricated in 0.18- CMOS to demonstrate the concept. View full abstract»

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  • Gain-Enhanced Distributed Amplifier Using Negative Capacitance

    Publication Year: 2010 , Page(s): 2834 - 2843
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (907 KB) |  | HTML iconHTML  

    This paper presents a new high-gain structure for the distributed amplifier. Negative capacitance cells are exploited to ameliorate the loading effects of parasitic capacitors of gain cells in order to improve the gain of the distributed amplifier while keeping the desired bandwidth. In addition, the negative capacitance circuit creates a negative resistance that can be used to increase the amplifier bandwidth. Implemented in 0.13-μm IBM's CMRF8SF CMOS, the proposed six-stage distributed amplifier presents an average gain of 13.2 dB over a bandwidth of 29.4 GHz. The measured input return loss is less than -9 dB and the output return loss is less than -9.5 dB over the entire bandwidth. With a chip area of 1.5 mm × 0.8 mm, the amplifier consumes 136 mW from a 1.5-V dc power supply. View full abstract»

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  • A 5-Gbit/s CMOS Optical Receiver With Integrated Spatially Modulated Light Detector and Equalization

    Publication Year: 2010 , Page(s): 2844 - 2857
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6165 KB) |  | HTML iconHTML  

    This paper presents an optical receiver with a monolithically integrated photodetector in 0.18-μm CMOS technology using a combination of spatially modulated light (SML) detection and an analog equalizer. A transimpedance amplifier employing negative Miller capacitance is introduced to increase its bandwidth without causing gain peaking. To provide sufficient reverse-bias voltage to the photodetector's p-n junction, the transimpedance amplifier is operated with a 3.3-V supply, while the rest of the circuit blocks is powered with a 1.8-V supply. The on-chip SML detector achieves a net responsivity of 0.052 A/W. Occupying a core area of 0.72 mm2, the fully integrated optical receiver achieves 4.25 and 5 Gbits/s with power consumption values of 144 and 183 mW, respectively. View full abstract»

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  • A Switching-Based Phase Noise Model for CMOS Ring Oscillators Based on Multiple Thresholds Crossing

    Publication Year: 2010 , Page(s): 2858 - 2869
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1328 KB) |  | HTML iconHTML  

    For a ring oscillator with an arbitrary voltage swing, core transistors in delay cells typically move between saturation and triode region This can result in the overall timing jitter being dominated by timing jitter accumulated within a particular region. Based on multiple thresholds crossing concept, a new and more accurate way of handling such region change is developed. Specifically any crossing between two such regions, prior to the actual crossing of the threshold that triggers the next stage delay cell, is treated as an internal threshold crossing. The timing jitter is then the sum (in the rms sense) of the timing jitter accumulated across multiple thresholds crossing. The model agrees to within 2 dB with measurements, on differential pair based (both replica bias and physical resistor load) and current starved inverter based ring oscillators, fabricated in CMOS. Design insights from the model show that, for a differential pair ring oscillator that is originally designed with a given voltage swing such that the input transistors can be in triode, if voltage swing is reduced so that input transistors just do not go into triode, phase noise can be improved. A 7-dB phase noise improvement on an example design using a replica bias differential ring oscillator, based on this insight, is demonstrated. View full abstract»

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  • A 10–Bit 1.6-GS/s 27-mW Current-Steering D/A Converter With 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS

    Publication Year: 2010 , Page(s): 2870 - 2879
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1357 KB) |  | HTML iconHTML  

    This paper presents a 10-bit 5-5 segmented current- steering digital-to-analog converter implemented in a standard 130-nm CMOS technology. It achieves full-Nyquist performance up to 1 GS/s and maintains 54-dB SFDR over a 550-MHz output bandwidth up to 1.6 GS/s. The power consumption for a near-Nyquist output signal sampled at 1.6 GS/s equals 27 mW. To enable the presented performance a design strategy is proposed that introduces a switch-driver power consumption aware analysis of the switched current cell. The analysis of the major distortion mechanisms in the switched current cell allows the derivation of a design strategy for maximum linearity. This strategy is extended to include the power consumption of the switch drivers in function of the switched current cell design. To minimize the digital power consumption, low-power implementations of the thermometer decoder and switch driver circuits are introduced. View full abstract»

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  • Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops

    Publication Year: 2010 , Page(s): 2880 - 2889
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1695 KB) |  | HTML iconHTML  

    Supply noise affects the jitter performance of ring oscillator-based phase-locked loops (PLLs) significantly. While the focus of much of the prior art is on supply noise in oscillators, this paper illustrates that supply noise in other building blocks also contribute significantly to PLL output jitter. Analytical expressions for supply-noise sensitivities are derived for each of the circuit blocks used in the PLL and insight into the mechanism through which supply noise appears at the PLL output is provided. Efficient supply-regulation schemes that combine a split-tuned PLL architecture with an optimized low-dropout regulator to achieve better than -22 dB of worst case supply-noise sensitivity for the whole PLL are presented. Fabricated in a 0.18 μm digital CMOS process, the prototype PLL occupies an area of 0.18 μm and operates from a 1.8 V supply. At 1.5 GHz, the total power consumption is 3.3 mW, of which 0.54 mW is consumed in the regulators. The measured output peak-to-peak jitter is 33 ps and 41 ps with no supply noise and with a 100-mV amplitude supply noise tone injected at the worst case noise frequency, respectively. View full abstract»

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  • Self-Reconfigurable Channel Data Buffering Scheme and Circuit Design for Adaptive Flow Control in Power-Efficient Network-on-Chips

    Publication Year: 2010 , Page(s): 2890 - 2903
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3034 KB) |  | HTML iconHTML  

    This paper presents a self-reconfigurable channel data buffering scheme and circuit design for next-generation network-on-chips (NoCs). The design is optimized for power efficiency and data throughput, from system to circuit level. During network congestion, the buffering scheme realizes adaptive flow control by reconfiguring the channel buffers for online data storage. Once congestion is alleviated, data transmission resumes from the foremost buffer stage, thereby improving NoC throughput. It also achieves system-level power optimization through an integrated hardware-software codesign approach. Using software techniques such as dynamic voltage and frequency scaling, optimal voltages and frequencies are provided to the system through a hardware-based single-inductor multiple-output dc-dc converter platform. Meanwhile, power dissipation is further minimized through switched-capacitor delay control modules. A CMOS IC prototype has been fabricated, with 16-bit data transmission capability. It demonstrates 58.9% power saving over conventional designs. To achieve the same throughput, it consumes only 45.4% power of the best prior art. The flexibility of the buffering scheme, along with the integrated power management solution, allows it to be applied to most existing commercial NoC architectures. View full abstract»

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  • Equivalent Circuits for the PNS2 Sampling Scheme

    Publication Year: 2010 , Page(s): 2904 - 2914
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (613 KB) |  | HTML iconHTML  

    Periodic nonuniform sampling of second order (PNS2) involves two periodic sequences with the same period. This sampling scheme has been shown to remove aliasing. Moreover, under particular conditions on their spectral band (or spectral support), exact reconstruction of functions can be derived from their PNS2. This paper more generally deals with the best mean-square interpolation for stationary processes with any known power spectrum, from PNS2 and, possibly, with aliasing. We show that the best estimation is based upon particular linear filters, which depend on the gap between both sampling sequences. The mean-time error also depends on this gap. The errorless interpolation is a particular case. It requires the knowledge of the spectral support rather than the power-spectrum values. View full abstract»

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  • Discriminating Multiple Nearby Targets Using Single-Ping Ultrasonic Scene Mapping

    Publication Year: 2010 , Page(s): 2915 - 2924
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1459 KB) |  | HTML iconHTML  

    We present a software simulation and a hardware proof of concept for a compact low-power lightweight ultrasonic echolocation design that is capable of imaging a 120 field of view with a single ping. The sensor uses a single transmitter and a linear array of ten microphones, followed by a bank of eight spatiotemporal filters to determine the bearing angle of returned echoes. The sensor is capable of detecting multiple objects with a single omnidirectional ping, even if their echoes interfere with each other at the microphone array. The hardware implementation detects the bearing of nearby objects with an rms accuracy of 1.6° and can reliably detect a 70-cm-long 5-cm-diameter metal table leg at a range of 3 m. Stronger reflectors, such as building corners, can be reliably detected at a range of 9 m. View full abstract»

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  • Closed-Form Design of Maximally Flat IIR Hilbert Transformer With Integer Delay

    Publication Year: 2010 , Page(s): 2925 - 2937
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (657 KB) |  | HTML iconHTML  

    This paper presents the closed-form designs of an infinite-impulse-response (IIR) Hilbert transformer with an integer delay. The maximally flat criterion is applied at the midband frequency π/2. These designs are further categorized into eight types according to the filter orders and the delay values being even or odd. Their coefficients can be explicitly solved in closed form. A recursive relation also exists, facilitating the computation of these coefficients. Moreover, under the suggested relations and formula for the design parameters based on the Eneström-Kakeya theorem, we can obtain a satisfactory stable IIR Hilbert transformer. View full abstract»

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  • Nullcline-Based Design of a Silicon Neuron

    Publication Year: 2010 , Page(s): 2938 - 2947
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1199 KB) |  | HTML iconHTML  

    In this paper, we describe the design of a silicon neuron that exhibits type-I neural excitability, i.e., the frequency of spiking of the neuron approaches arbitrarily close to zero as the input current is reduced. Our design creates a conductance-based silicon model that can exhibit a saddle-node bifurcation. We present simulations and measured data from circuits fabricated in 0.35-μm CMOS that demonstrate both saddle-node bifurcation on invariant circle and saddle-homoclinic bifurcation. In our design, concepts from nonlinear dynamics are used not only for the analysis but also for the synthesis of the circuit. This leads to a nullcline-based methodology that enables a strategic approach for biasing the circuit in the desired regime in parameter space. Combined with the ability to set local biases (e.g., floating gates), this methodology should largely minimize mismatch in arrays of silicon neurons of this kind. The presented circuit is the most power efficient design reported so far, and we hope to fabricate larger arrays of this neuron to explore network behavior. View full abstract»

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  • Discrete-Time Modeling and Stability Analysis of Periodic Orbits With Sliding for Switched Linear Systems

    Publication Year: 2010 , Page(s): 2948 - 2955
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (474 KB) |  | HTML iconHTML  

    This paper establishes a discrete-time model and presents an exact method of stability analysis for periodic orbits containing a segment of sliding orbit for switched linear systems. Sliding dynamical equations are obtained by using Utkin's equivalent control method. Sliding mapping and impact mapping are obtained by solving the respective differential equations. A generalized discrete-time mapping for a cycle is derived for three operating scenarios. The coordinates of the periodic orbit points, inflow and outflow sliding regions, and the corresponding Jacobians are obtained. Theoretical analysis and simulation results for a third-order relay-feedback system and a second-order autonomous oscillating circuit are presented to illustrate the proposed model and method. View full abstract»

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  • Analysis and Design of Injection-Locked Frequency Dividers by Means of a Phase-Domain Macromodel

    Publication Year: 2010 , Page(s): 2956 - 2966
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1102 KB) |  | HTML iconHTML  

    This paper describes an original method to estimate the locking ranges of injection-locked frequency dividers (ILFDs) and their sensitivity to variations in parameter values. The synchronization capability of a given oscillator architecture with respect to possible injection points is explored by applying small-amplitude signals and adopting a phase-domain macromodel based on the paradigm of the perturbation projection vector. It is shown that the method provides synthesis information and guidelines that help to improve the ILFD design process and the selection of a proper injection strategy. View full abstract»

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  • Exponential Synchronization of Complex Delayed Dynamical Networks With Switching Topology

    Publication Year: 2010 , Page(s): 2967 - 2980
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1329 KB) |  | HTML iconHTML  

    This paper studies the local and global exponential synchronization of a complex dynamical network with switching topology and time-varying coupling delays. By using stability theory of switched systems and the network topology, the synchronization of such a network under some special switching signals is investigated. Firstly, under the assumption that all subnetworks are self-synchronizing, a delay-dependent sufficient condition is given in terms of linear matrix inequalities, which guarantees the solvability of the local synchronization problem under an average dwell time scheme. Then this result is extended to the situation that not all subnetworks are self-synchronizing. For the latter case, in addition to average dwell time, an extra condition on the ratio of the total activation time of self-synchronizing and nonsynchronizing subnetworks is needed to achieve synchronization of the entire switched network. The global synchronization of a network whose isolate dynamics is of a particular form is also studied. Three different examples of delayed dynamical networks with switching topology are given, which demonstrate the effectiveness of obtained results. View full abstract»

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  • A Wavelet-Collocation-Based Trajectory Piecewise-Linear Algorithm for Time-Domain Model-Order Reduction of Nonlinear Circuits

    Publication Year: 2010 , Page(s): 2981 - 2990
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (564 KB) |  | HTML iconHTML  

    Trajectory piecewise-linearization-based reduced- order macromodeling methods have been proposed to characterize the time-domain behaviors of large strongly nonlinear systems. However, all these methods rely on frequency-domain model-order-reduction (MOR) methods for linear systems. Therefore, the accuracy of the reduced-order models in time domain cannot always be guaranteed and controlled. In this paper, a wavelet-collocation-based trajectory piecewise-linear approach is proposed for time-domain MOR of strongly nonlinear circuits. The proposed MOR method is performed in time domain and is based on a wavelet-collocation method. Compared with nonlinear MOR methods in frequency domain, the proposed method in time domain maintains higher accuracy for modeling transient characteristics of nonlinear circuits, which are very important in macromodeling and transient analysis for nonlinear circuits. Furthermore, a nonlinear wavelet companding technique is developed to control the modeling error in time domain, which is useful for balancing the overall modeling error over the whole time region and improving the simulation efficiency at higher level. The numerical results show that the proposed method has high macromodeling accuracy in time domain, and the modeling-error distribution in time domain can be efficiently controlled by the wavelet companding technique. View full abstract»

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  • Synchronization Between Two Complex Dynamical Networks Using Scalar Signals Under Pinning Control

    Publication Year: 2010 , Page(s): 2991 - 2998
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (663 KB) |  | HTML iconHTML  

    In this paper, a new scheme for synchronization between two or more complex networks is proposed using scalar signals under pinning control. Unlike common synchronization schemes, where all states of the driving networks are transmitted to the response network and all the nodes in the response network are required to be controlled, here, it is suggested that only a few nodes in the response network are controlled and only a few scalar signals are required to be transmitted from the driving network to the response one. Some criteria for synchronization between two or more complex dynamical networks are given in the form of linear matrix inequality. Furthermore, how to choose the pinned nodes according to the network topology is discussed by a numerical simulation method. Some typical network configurations are simulated, and the simulation results show that the proposed synchronization scheme is effective for the synchronization between two or more complex networks. View full abstract»

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  • Linear Systems With Medium-Access Constraint and Markov Actuator Assignment

    Publication Year: 2010 , Page(s): 2999 - 3010
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (596 KB) |  | HTML iconHTML  

    This paper investigates a type of systems controlled over a communication network that can only accommodate a subset of actuators at any time. The medium-access status of actuators is event driven by a stochastic process modeled as a Markov chain. A methodology of analysis and control synthesis is established using theories in time-delay systems and Markovian jumping systems. Specifically, in the context of asymptotic mean-square stability, a state feedback control approach is derived by transforming the vector system into a scalar representation first and then using on it a stability criterion provided for scalar linear time-delay systems. The results are given in terms of a delay-dependent scalar inequality and a simple matrix inequality based on a couple of scalar decision variables, which are easily solvable using the newly proposed quasi-convex optimization algorithm. The corresponding results for uncertain linear systems are also given. Meanwhile, a design approach in the sense of stochastic stability in probability is presented using a Lyapunov-like method, with the mode-dependent results being given in the form of a set of coupled matrix differential inequalities and a martingale probability inequality. Numerical examples have shown the usefulness of the proposed results. View full abstract»

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  • A Discrete-Time FFT Processor for Ultrawideband OFDM Wireless Transceivers: Architecture and Behavioral Modeling

    Publication Year: 2010 , Page(s): 3011 - 3022
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (683 KB) |  | HTML iconHTML  

    A discrete-time (DT) fast Fourier transform (FFT) processor which enables an architectural improvement to ultrawide-bandwidth orthogonal frequency-division multiplexing (OFDM) receivers for use in low-power handheld applications is presented. The new architecture performs FFT demodulation of the OFDM signal in the DT signaling domain before analog-to-digital conversion. The approach significantly reduces the required number of bits in the analog-to-digital converter (ADC) while increasing receiver linearity and providing improved handling of narrow-band blockers. The processor is first implemented in simulation using a top-down methodology based on behavioral models which are developed to describe the circuit functions of the DT FFT processor. System simulation results show that the processor can be implemented with DT CMOS circuits having typical nonidealities while outperforming equivalent all-digital FFT processors. An improvement in dynamic range in the FFT processor and ADC from 35 to 54 dB is demonstrated through simulation. View full abstract»

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  • Comparative Studies of Common Fix-Frequency Controls for Reference Tracking and Enhancement by End-Point Prediction

    Publication Year: 2010 , Page(s): 3023 - 3034
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2950 KB) |  | HTML iconHTML  

    This paper analyzes the dynamics of reference tracking in switched-mode power converters in terms of both large-signal and small-signal perspectives. Common control schemes, namely, voltage mode, current mode, and V2-control, are compared for their performance in reference tracking. For small-signal analysis, loop gains and reference-to-output transfer functions are analytically derived and verified by the proposed Matlab-based frequency response simulator. In the case of multiple-loop control like V2-control, different loop gains are clarified for their application in load transient or reference tracking. Practical circuit-level design considerations are given to current-mode control for achieving fast reference tracking, while end-point prediction (EPP) is used to improve V2-control, which is inherently slow in reference tracking. The effect of EPP on transfer function is then explained in details. A V2-controlled buck converter with EPP is fabricated. The measured reference-tracking response shows ten times improvement in tracking speed and verifies the effectiveness of EPP in V2-control. View full abstract»

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  • IEEE Transactions on Circuits and Systems—I: Regular Papers Information for authors

    Publication Year: 2010 , Page(s): 3035
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  • Quality without compromise [advertisement]

    Publication Year: 2010 , Page(s): 3036
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2010 , Page(s): C3
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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras