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IET Computers & Digital Techniques

Issue 6 • Date November 2010

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Displaying Results 1 - 6 of 6
  • Instruction cache tuning for embedded multitasking applications

    Publication Year: 2010, Page(s):439 - 457
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (959 KB)

    With the advent of mobile and handheld devices, power consumption in embedded systems has become a key design issue. Recently, it has been shown that cache requirements of the applications vary widely and a significant amount of energy can be saved by tuning the cache parameters according to the needs of the application. To this end, techniques have been proposed to tune the cache for single-task-... View full abstract»

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  • Generic approach for hardening state machines against strong adversaries

    Publication Year: 2010, Page(s):458 - 470
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (349 KB)

    Most of the countermeasures against active fault injection attacks focus on securing the datapath of the cryptographic circuits. However, control unit security thus far has been neglected except for a few scattered references and there is not much work done to secure finite state machines (FSMs) against advanced attackers. In this study, the authors propose a novel methodology to remove the vulner... View full abstract»

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  • Very large scale integration architecture for integer wavelet transform

    Publication Year: 2010, Page(s):471 - 483
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (981 KB)

    In this study, the design of an integer lifting wavelet transform (IWT) architecture is presented. An efficient design method is proposed to construct a programmable integrated architecture in very large scale integration (VLSI) technology that can operate as a forward or backward IWT at speeds up to 194.3 MHz. The layout of the integrated VLSI structure is simple, modular and cascadable for compu... View full abstract»

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  • On-chip memory space partitioning for chip multiprocessors using polyhedral algebra

    Publication Year: 2010, Page(s):484 - 498
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (916 KB)

    One of the most important issues in designing a chip multiprocessor is to decide its on-chip memory organisation. While it is possible to design an application-specific memory architecture, this may not necessarily be the best option, in particular when storage demands of individual processors and/or their data sharing patterns can change from one point in execution to another for the same applica... View full abstract»

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  • Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks

    Publication Year: 2010, Page(s):499 - 514
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1207 KB)

    A dual-edge sense amplifier flip-flop (DE-SAFF) for resonant clock distribution networks (CDNs) is proposed. The clocking scheme used to enable dual-edge triggering in the proposed SAFF reduces short circuit power by allowing the precharging transistors to be switched on only for a portion of the clock period. The extracted circuit layout of the proposed DE-SAFF has been simulated in STMicroelectr... View full abstract»

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  • VHDL architecture for IEC 61499 function blocks

    Publication Year: 2010, Page(s):515 - 524
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (924 KB)

    IEC 61499 runtime systems to-date have focussed on software implementations deployed to various micro-processors. This study proposes a novel and viable architecture allowing IEC 61499 models to be deployed as custom logic within a field programmable gate arrays (FPGAs). A complier/translator has been developed, by the authors, capable of translating IEC 61499 models to their very-high-speed integ... View full abstract»

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IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems.

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