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Electron Devices, IEEE Transactions on

Issue 12 • Date Dec. 2010

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Displaying Results 1 - 25 of 51
  • Table of contents

    Page(s): C1 - 3194
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  • IEEE Transactions on Electron Devices publication information

    Page(s): C2
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  • Kudos to our reviewers

    Page(s): 3195
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  • Golden List of Reviewers for 2010

    Page(s): 3196 - 3220
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  • Confidentiality of the review process

    Page(s): 3221
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  • On the Possibility of Obtaining MOSFET-Like Performance and Sub-60-mV/dec Swing in 1-D Broken-Gap Tunnel Transistors

    Page(s): 3222 - 3230
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1211 KB) |  | HTML iconHTML  

    Tunneling field-effect transistors (TFETs) have gained a great deal of interest recently due to their potential to reduce power dissipation in integrated circuits. One major challenge for TFETs so far has been to achieve high drive currents, which is a prerequisite for high-performance operation. In this paper, we explore the performance potential of a 1-D TFET with a broken-gap heterojunction source injector using dissipative quantum transport simulations based on the nonequilibrium Green's function formalism, as well as the carbon nanotube band structure as the model 1-D material system. We provide detailed insights into broken-gap TFET (BG-TFET) operation and show that it can, indeed, produce less than 60 mV/dec subthreshold swing at room temperature, even in the presence of electron-phonon scattering. The 1-D geometry is recognized to be uniquely favorable due to its superior electrostatic control, reduced carrier thermalization rate, and beneficial quantum confinement effects that reduce the off-state leakage below the thermionic limit. Because of higher source injection compared to staggered-gap and homojunction geometries, BG-TFET delivers superior performance that is comparable to MOSFET's. BG-TFET even exceeds the MOSFET performance at lower supply voltages (VDD), showing promise for low-power/high-performance applications. View full abstract»

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  • Quantum Effects on the Gate Capacitance of Trigate SOI MOSFETs

    Page(s): 3231 - 3238
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (964 KB) |  | HTML iconHTML  

    Scaling effects on the gate capacitance of trigate MOS field-effect transistors are studied by means of analytical models and numerical self-consistent solutions of the 2-D Schrödinger and Poisson equations. Special attention is paid to the quantum capacitance, which is related to the density of states. We show that, although the quantum capacitance strongly decreases when the channel dimensions are scaled, the gate capacitance is not reduced relative to the oxide capacitance in trigate MOS structures. This is due to the fact that both the oxide capacitance and the quantum capacitance scale with the channel cross section. From Schrödinger-Poisson simulations, we actually observe a relative increase in the gate capacitance when the silicon cross section is scaled below 7 nm × 7 nm, whereas the opposite trend is obtained from classical calculations. We relate this mainly to the differences between quantum-mechanical and classical electron distributions in real space. Quantization effects on the quantum capacitance are found to have less effect on the gate capacitance except for very small silicon cross sections in the order of 2 nm × 2 nm. View full abstract»

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  • Pseudospectral Methods for the Efficient Simulation of Quantization Effects in Nanoscale MOS Transistors

    Page(s): 3239 - 3249
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    This paper presents an in-detail investigation of the possible advantages related to the use of the pseudospectral (PS) method for the efficient description of the carrier quantization in nanoscale n- and p-MOS transistors. To this purpose, we have implemented, by using both the finite-difference (FD) and PS methods, self-consistent Schrödinger-Poisson solvers for both a 2-D hole gas described by a k ·p Hamiltonian (suitable for p-MOSFETs) and a 1-D electron gas in the effective-mass approximation (for n-type fin-shaped FETs and nanowire FETs). The PS and FD methods have been systematically compared in terms of the CPU time and the number of discretization points by monitoring not only the subband energies in the low-dimensional carrier gas but also the calculation of some scattering matrix elements that are critically important for the transport modeling. Our results indicate a remarkable reduction in the CPU time for the PS method with respect to the FD method, which makes the PS method very attractive for the modeling of the carrier quantization in nanoscale MOSFETs. View full abstract»

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  • Comparative Study of FinFET Versus Quasi-Planar HTI MOSFET for Ultimate Scalability

    Page(s): 3250 - 3256
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (390 KB) |  | HTML iconHTML  

    The FinFET is compared against the quasi-planar trigate bulk MOSFET with high-permittivity (high- k) dielectric trench isolation (HTI MOSFET) for low-standby-power applications, at dimensions near the end-of-roadmap (11-nm half-pitch). It is found that the optimal transistor structure depends on the fin aspect ratio (AR) and the HTI dielectric constant εHTI: for sufficiently high εHTI, the HTI MOSFET can provide comparable or lower delay as the FinFET, for AR up to ~2.5. Thus, the development of high-k dielectric and/or high-AR fin formation technologies will ultimately determine which transistor design is more advantageous. View full abstract»

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  • Transient Simulation of Delay and Switching Effects in Phase-Change Memories

    Page(s): 3257 - 3264
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    The transient simulation of threshold switching in phase-change memory (PCM) devices is essential for the prediction and optimization of cell behavior depending on the circuit parameters and for the understanding of the ultimate limit of operation speed. This paper presents a simulation study of threshold switching in PCM devices aimed at investigating the role of delay and switching times in cell behavior. The analytical Poole-Frenkel model for conduction and the energy gain model for threshold switching are used to evaluate the transient effects. The current and field transients at the basis of the switching phenomenon are shown and discussed with the aid of the numerical model. The impact of cell parasitics, in particular the parallel capacitance, is finally addressed. View full abstract»

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  • Demonstration of Intrinsic Tristability in Double-Barrier Resonant Tunneling Diodes With the Wigner Transport Equation

    Page(s): 3265 - 3274
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    The operation of double-barrier resonant tunneling diodes (RTDs) is investigated through self-consistent numerical solution of the Wigner transport equation. Prevalent boundary conditions are demonstrated to lead to unphysical boundary layers in electrostatically self-consistent calculations. New boundary conditions based on nonequilibrium statistics are proposed and validated. Unphysical solutions are also associated with the application of the popular Boltzmann collision operator in the limit of high electron density. An original formulation of the collision operator in the relaxation time approximation is proposed leading to proper asymptotic behavior in both limits of the relaxation time. Coupled solutions of the Wigner transport equation and the Poisson equation for an RTD structure reveal current to be a continuous but multivalued function of applied bias and tristability to be an intrinsic property of device operation. View full abstract»

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  • A Scalable SCR Compact Model for ESD Circuit Simulation

    Page(s): 3275 - 3286
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    A scalable compact model for SCR-based electrostatic discharge (ESD) protection devices is presented. This model captures the effect that layout spacing has on SCR characteristics, such as holding voltage and trigger current. The model also captures both the delayed turn-on of the SCR, which results in large voltage overshoots during fast rise-time ESD events and the charge removal mechanisms that underlie the turn-off transient. Bias and time dependences of SCR on-resistance are captured with a resistance model that accounts for self-heating. View full abstract»

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  • A Low-Field Mobility Model for Bulk and Ultrathin-Body SOI p-MOSFETs With Different Surface and Channel Orientations

    Page(s): 3287 - 3294
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (614 KB) |  | HTML iconHTML  

    An easy-to-implement hole mobility model, which accurately predicts low-field mobility in bulk MOSFETs and ultrathin-body (UTB) silicon-on-insulator FETs with different crystal orientations, is developed. The model accounts for the influence of the surface orientation and the inplane current-flow direction on effective masses, subband repopulation, and scattering rates. The effects induced by extremely small silicon thicknesses are also addressed. A good agreement with the experimental mobilities of bulk and UTB FETs with silicon thicknesses from 60 nm to values as small as about 2.7 and 2.3 nm is demonstrated for devices with (100) and (110) substrates, respectively. View full abstract»

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  • Ge p-MOSFETs With Scaled ALD \hbox {La}_{2} \hbox {O}_{3}/\hbox {ZrO}_{2} Gate Dielectrics

    Page(s): 3295 - 3302
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    Dielectric thin films of La2O3/ZrO2 deposited by atomic layer deposition (ALD) are investigated to be employed in Ge Schottky barrier p-MOSFETs. La2O3 is used as a thin passivation layer and is capped by atomic-layer-deposited ZrO2 as a gate dielectric. As the gate contact TiN capped by W is applied, midgap-level trap densities of ~ 3-4 × 1012 eV-1 cm-2 and subtreshold slopes down to 115-120 mV/dec are achieved. The devices show negative threshold voltages of -0.5 to -0.6 V, as well as peak hole mobility values of ~ 50-75 cm2/V · s. Equivalent oxide thickness (EOT) is reduced to 0.96 nm upon postmetallization annealing without degrading the interface properties. The results show the scaling potential of the ALD La2O3 interlayer capped with ZrO2 gate dielectrics for the integration into sub-1-nm EOT Ge p-MOSFET devices. View full abstract»

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  • Harmonic Distortion of Unstrained and Strained FinFETs Operating in Saturation

    Page(s): 3303 - 3311
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (452 KB) |  | HTML iconHTML  

    The harmonic distortion (HD) exhibited by unstrained and biaxially strained fin-shaped field-effect transistors operating in saturation as single-transistor amplifiers has been investigated for devices with different channel lengths L and fin widths Wfin. The study has been performed through device characterization, 3-D device simulations, and modeling. Nonlinearity has been evaluated in terms of second- and third-order HDs (HD2 and HD3, respectively), and a discussion on its physical sources has been carried out. Also, the influence of the open-loop voltage gain AV in HD has been observed. View full abstract»

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  • Impact of Surface Orientation on the Sensitivity of FinFETs to Process Variations—An Assessment Based on the Analytical Solution of the Schrödinger Equation

    Page(s): 3312 - 3317
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (665 KB) |  | HTML iconHTML  

    This paper investigates the impact of surface orientation on Vth sensitivity to process variations for Si and Ge fin-shaped field-effect transistors (FinFETs) using an analytical solution of the Schrödinger equation. Our theoretical model considers the parabolic potential well due to short-channel effects and, therefore, can be used to assess the quantum-confinement effect in short-channel FinFETs. Our study indicates that, for ultrascaled FinFETs, the importance of channel thickness (tch) variations increases due to the quantum-confinement effect. The Si-(100) and Ge-(111) surfaces show lower Vth sensitivity to the tch variation as compared with other orientations. On the contrary, the quantum-confinement effect reduces the Vth sensitivity to the Leff variation, and Si-(111) and Ge-(100) surfaces show lower Vth sensitivity as compared with other orientations. Our study may provide insights for device design and circuit optimization using advanced FinFET technologies. View full abstract»

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  • Self-Aligned Silicidation of Surround Gate Vertical MOSFETs for Low Cost RF Applications

    Page(s): 3318 - 3326
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    We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully integrated with a Fillet Local OXidation (FILOX) process, which thereby delivers low overlap capacitance and high-drive-current vertical devices. Silicided 80-nm vertical n-channel devices fabricated using 0.5-μm lithography are compared with nonsilicided devices. A source-drain (S/D) activation anneal of 30 s at 1100°C is shown to deliver a channel length of 80 nm, and the silicidation gives a 60% improvement in drive current in comparison with nonsilicided devices. The silicided devices exhibit a subthreshold slope (S) of 87 mV/dec and a drain-induced barrier lowering (DIBL) of 80 mV/V, compared with 86 mV/dec and 60 mV/V for nonsilicided devices. S-parameter measurements on the 80-nm vertical nMOS devices give an fT of 20 GHz, which is approximately two times higher than expected for comparable lateral MOSFETs fabricated using the same 0.5-μm lithography. Issues associated with silicidation down the pillar sidewall are investigated by reducing the activation anneal time to bring the silicided region closer to the p-n junction at the top of the pillar. In this situation, nonlinear transistor turn-on is observed in drain-on-top operation and dramatically degraded drive current in source-on-top operation. This behavior is interpreted using mixed-mode simulations, which show that a Schottky contact is formed around the perimeter of the pillar when the silicided contact penetrates too close to the top S/D junction down the side of the pillar. View full abstract»

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  • DC Characteristics of InAlAs/InGaAsSb/InGaAs Double Heterojunction Bipolar Transistors

    Page(s): 3327 - 3332
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    DC electrical characteristics of a series of InAlAs/InGaAsSb/InGaAs double heterojunction bipolar transistors (DHBTs) that are grown on InP by molecular beam epitaxy are reported and analyzed. The InGaAsSb base of the transistors leads to a type-I base-emitter junction and a type-II base-collector junction, resulting in unique device characteristics, such as low turn-on voltage, low crossover current, and constant current gain over a wide current range. In addition, the DHBTs exhibit rather high current gains despite the use of a heavily doped thick InGaAsSb base layer. This indicates the long minority carrier lifetime of the InGaAsSb material. A high current gain over base sheet resistance ratio is, thus, realized with these novel DHBTs. View full abstract»

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  • Limitations of Field Plate Effect Due to the Silicon Substrate in AlGaN/GaN/AlGaN DHFETs

    Page(s): 3333 - 3339
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    We investigated the limitations of the field plate (FP) effect on breakdown voltage VBD that is due to the silicon substrate in AlGaN/GaN/AlGaN double heterostructures field-effect transistors. In our previous work, we showed that in devices with large gate-drain distance (LGD > 8 μm), the breakdown voltage does not linearly increase with LGD because of a double leakage path between the silicon substrate and the metal contacts, which makes the device break at the silicon interface. In this paper, we showed that the effect of the FP for such large LGD is not significant because the breakdown is still dominated by the silicon substrate. The increase in VBD due to the FP is significant only for devices with small gate-drain distances (LGD <; 8 μm). Indeed we show that for such small LGD the increase in the breakdown voltage is more than double, whereas for larger LGD, this is only about 10%. Simulations of AlGaN/GaN/AlGaN devices for small LGD are carried out with different FP lengths and passivation thickness in order to study the electric field distribution. View full abstract»

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  • Elimination of Current Blocking in Ternary InAlAs-InGaAs-InAlAs Double Heterojunction Bipolar Transistors

    Page(s): 3340 - 3347
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (651 KB) |  | HTML iconHTML  

    Molecular beam epitaxy-grown wafers are used to fabricate all ternary In0.52Al0.48As-In0.53Ga0.47As-In0.52Al0.48As double heterojunction bipolar transistors (DHBTs) with knee voltages of less than 1 V, showing no current blocking characteristic even at current densities of 200 kA/cm2. A set of wafers with a judicious combination of doping interface dipoles and composite collector designs were grown, and devices with a wide range of emitter areas from 20 × 20 down to 1 × 5 μm2 were fabricated to investigate the effects of the different epitaxial and geometrical design tradeoffs that culminated in an optimum design that is able to achieve high breakdown and high current gain without introducing current blocking. Despite the use of a heavy dipole doping of 4 × 1018 cm-3, a breakdown voltage BVCEO of 5.8 V at 0.2 kA/cm2 is achieved at room temperature. We believe this to be the first demonstration of an all-ternary large band gap InAlAs-InGaAs-InAlAs DHBTs with no current blocking up to a high current density of 200 kA/cm2. These new DHBTs that use only ternary alloys may lead to simplified device growth and fabrication options and give deeper understanding of the design tradeoffs in these structures. View full abstract»

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  • Comparison of N- and Ga-Face GaN HEMTs Through Cellular Monte Carlo Simulations

    Page(s): 3348 - 3354
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB) |  | HTML iconHTML  

    We compare the performance of GaN HEMT devices based on the established Ga-face technology and the emerging N-face technology. Starting from a state-of-the-art N-face device, we obtain the analogous Ga-face layout imposing the constraint of the same channel charge in both structures, and then, we simulate both the configurations with our full-band cellular Monte Carlo simulator, which includes the full details of the band structure and the phonon spectra. Moreover, we define a modeling approach based on gate-to-2-D electron gas distance and capacitance discussions, which allows a fair comparison between the N- and Ga-face technologies. Full direct current and RF simulations were performed and compared with available experimental data for the N-face device in order to calibrate the few adjustable simulator parameters. Our simulations indicate that N-face GaN HEMTs exhibit improved RF performance with respect to Ga-face devices. Furthermore, the use of an AlN layer in N-face devices results in a reduced alloy scattering and offers a strong back-barrier electron confinement to mitigate short-channel effects, thus improving the cutoff frequency for highly scaled devices. View full abstract»

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  • Processing Techniques for Monolithic Interconnection of Solar Cells at Wafer Level

    Page(s): 3355 - 3360
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (777 KB) |  | HTML iconHTML  

    Monolithic interconnected modules are large-area high-voltage photovoltaic devices that are realized through solar cell segments that are series-connected via interconnection trenches during wafer processing. This paper investigates different processing techniques, giving detailed information about each processing sequence. In the first approach, a wet chemical etching procedure and photo-defined polyimide as dielectric film is used, leading to minimal trench width of 86 μm. Furthermore, we examine the applicability of advanced processing techniques. An alternative dry-etching process using reactive ion etching in inductively coupled plasma is investigated. With this technique, smooth and near-vertical sidewalls could be achieved, whereas the undercuts in etching profile, which are inevitable when using wet chemical etching, could be avoided. Moreover, an accurate processing technique for plasma-enhanced chemical vapor deposited SiNx as a dielectric film for electrical isolation is presented. This allowed sufficient isolation to be achieved, as well as enabling precise structuring. With these advanced processing techniques, trench widths of 57 μm were realized, resulting in a reduction of area losses due to interconnection from 9% to below 6%. View full abstract»

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  • Characterization of Metamorphic GaAsP/Si Materials and Devices for Photovoltaic Applications

    Page(s): 3361 - 3369
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    GaAsyP1-y anion-sublattice compositionally graded buffers and device structures were grown directly on Si(100) substrates by way of a high-quality GaP integration layer, yielding GaAsP target layers having band gaps of photovoltaic interest (1.65-1.8 eV), free of antiphase domains/borders, stacking faults, and microtwins. GaAsyP1-y growths on both Si and GaP substrates were compared via high-resolution X-ray diffractometry of the metamorphic buffers and deep-level transient spectroscopy (DLTS) of p+-n diodes that are lattice matched to the final buffer layer. Structural analysis indicates highly efficient epitaxial relaxation throughout the entire growth structure for both types of samples and suggests no significant difference in physical behavior between the two types of samples. DLTS measurements performed on GaAsP diodes fabricated on both Si and GaP substrates reveal the existence of identical sets of traps residing in the n-type GaAsP layers in both types of samples: a single majority carrier (electron) trap, which is located at EC - 0.18&nbsp;eV, and a single minority carrier (hole) trap, which is located at EV + 0.71&nbsp;eV. Prototype 1.75-eV GaAsP solar cell test devices grown on GaAsyP1-y/Si buffers show good preliminary performance characteristics and offer great promise for future high-efficiency III-V photovoltaics integrated with Si substrates and devices. View full abstract»

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  • Improvement of Reliability of a Flexible Photoluminescent Display Using Organic-Based Materials

    Page(s): 3370 - 3376
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    In this paper, a prototype flexible photoluminescent display using organic materials based on a low-temperature process, in which all steps are carried out at under 100 °C, is proposed and fabricated, and the results are compared with those of a conventional plasma display. The proposed flexible photoluminescent display showed a bending radius of about 5 cm, and microplasma was successfully generated in the panel with about 80 V of sustain margin, and similar characteristics compared with that of conventional plasma displays were observed. In addition, the reliability of the proposed display was evaluated over a long period of more than 30 h, which corresponds to a real operation time of 150 h, considering the acceleration factor, to assess its lifetime. Mechanisms for discharge gas contamination, which is a serious problem for reliability, were proposed, and various methods were suggested and applied to improve the reliability of the proposed display. From the continuous measurement of the luminance of test panels, it was found that the various methods suggested here yielded improved reliability of the proposed flexible photoluminescent displays. Thus, the proposed flexible photoluminescent display shows potential as a future flexible display. View full abstract»

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  • Emission Time Constant of Exoelectron and Formative Delay Time Analyzed by Using Discharge Probability Distribution

    Page(s): 3377 - 3387
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1010 KB) |  | HTML iconHTML  

    A discharge probability model is proposed to analyze the stochastic distribution of the discharge delay time. The distribution is described as a hybrid function between the exponential and Gaussian distributions and their characteristic properties, such as the emission time constant of an exoelectron and the average and standard deviations of the formative delay time. The calculated results of the probability of a successful discharge show a good agreement with the experimental results measured in plasma display panels. The analytical protocol allows the discharge delay time to be accurately separated into the statistical and formative delay times. A thermal excitation and emission model is devised to analyze the effective number and the activation energy of electron emission sources (EESs) in a MgO layer using the emission time constant of an exoelectron. The effective number of the EES, i.e., 3.79 × 105 per cell, decreases after a long time interval because of the thermal excitation; thus, the emission time constant increases significantly. The effective number of the EES after 1000 h of sustain discharge decreases to 2.07 × 104 per cell, which is 0.055 times that before the sustain discharge. This degradation is explained by 2.6-4.3 times of increase in the density of electron traps due to the ion sputtering of noble gases against the MgO surface. The emission time constant is found to decrease to 0.45 times when the wall voltage near the MgO surface is increased by 11 V, which demonstrates that the exoelectron emission can be controlled by the electric field. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology