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# IEEE Transactions on Electron Devices

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Displaying Results 1 - 25 of 51

Publication Year: 2010, Page(s):C1 - 3194
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2010, Page(s): C2
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• ### Kudos to our reviewers

Publication Year: 2010, Page(s): 3195
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• ### Golden List of Reviewers for 2010

Publication Year: 2010, Page(s):3196 - 3220
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• ### Confidentiality of the review process

Publication Year: 2010, Page(s): 3221
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• ### On the Possibility of Obtaining MOSFET-Like Performance and Sub-60-mV/dec Swing in 1-D Broken-Gap Tunnel Transistors

Publication Year: 2010, Page(s):3222 - 3230
Cited by:  Papers (65)
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Tunneling field-effect transistors (TFETs) have gained a great deal of interest recently due to their potential to reduce power dissipation in integrated circuits. One major challenge for TFETs so far has been to achieve high drive currents, which is a prerequisite for high-performance operation. In this paper, we explore the performance potential of a 1-D TFET with a broken-gap heterojunction sou... View full abstract»

• ### Quantum Effects on the Gate Capacitance of Trigate SOI MOSFETs

Publication Year: 2010, Page(s):3231 - 3238
Cited by:  Papers (14)
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Scaling effects on the gate capacitance of trigate MOS field-effect transistors are studied by means of analytical models and numerical self-consistent solutions of the 2-D Schrödinger and Poisson equations. Special attention is paid to the quantum capacitance, which is related to the density of states. We show that, although the quantum capacitance strongly decreases when the channel dime... View full abstract»

• ### Pseudospectral Methods for the Efficient Simulation of Quantization Effects in Nanoscale MOS Transistors

Publication Year: 2010, Page(s):3239 - 3249
Cited by:  Papers (6)
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This paper presents an in-detail investigation of the possible advantages related to the use of the pseudospectral (PS) method for the efficient description of the carrier quantization in nanoscale n- and p-MOS transistors. To this purpose, we have implemented, by using both the finite-difference (FD) and PS methods, self-consistent Schrödinger-Poisson solvers for both a 2-D hole gas descr... View full abstract»

• ### Comparative Study of FinFET Versus Quasi-Planar HTI MOSFET for Ultimate Scalability

Publication Year: 2010, Page(s):3250 - 3256
Cited by:  Papers (1)  |  Patents (2)
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The FinFET is compared against the quasi-planar trigate bulk MOSFET with high-permittivity (high- k) dielectric trench isolation (HTI MOSFET) for low-standby-power applications, at dimensions near the end-of-roadmap (11-nm half-pitch). It is found that the optimal transistor structure depends on the fin aspect ratio (AR) and the HTI dielectric constant εHTI: for sufficient... View full abstract»

• ### Transient Simulation of Delay and Switching Effects in Phase-Change Memories

Publication Year: 2010, Page(s):3257 - 3264
Cited by:  Papers (12)
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The transient simulation of threshold switching in phase-change memory (PCM) devices is essential for the prediction and optimization of cell behavior depending on the circuit parameters and for the understanding of the ultimate limit of operation speed. This paper presents a simulation study of threshold switching in PCM devices aimed at investigating the role of delay and switching times in cell... View full abstract»

• ### Demonstration of Intrinsic Tristability in Double-Barrier Resonant Tunneling Diodes With the Wigner Transport Equation

Publication Year: 2010, Page(s):3265 - 3274
Cited by:  Papers (5)
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The operation of double-barrier resonant tunneling diodes (RTDs) is investigated through self-consistent numerical solution of the Wigner transport equation. Prevalent boundary conditions are demonstrated to lead to unphysical boundary layers in electrostatically self-consistent calculations. New boundary conditions based on nonequilibrium statistics are proposed and validated. Unphysical solution... View full abstract»

• ### A Scalable SCR Compact Model for ESD Circuit Simulation

Publication Year: 2010, Page(s):3275 - 3286
Cited by:  Papers (8)
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A scalable compact model for SCR-based electrostatic discharge (ESD) protection devices is presented. This model captures the effect that layout spacing has on SCR characteristics, such as holding voltage and trigger current. The model also captures both the delayed turn-on of the SCR, which results in large voltage overshoots during fast rise-time ESD events and the charge removal mechanisms that... View full abstract»

• ### A Low-Field Mobility Model for Bulk and Ultrathin-Body SOI p-MOSFETs With Different Surface and Channel Orientations

Publication Year: 2010, Page(s):3287 - 3294
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An easy-to-implement hole mobility model, which accurately predicts low-field mobility in bulk MOSFETs and ultrathin-body (UTB) silicon-on-insulator FETs with different crystal orientations, is developed. The model accounts for the influence of the surface orientation and the inplane current-flow direction on effective masses, subband repopulation, and scattering rates. The effects induced by extr... View full abstract»

• ### Ge p-MOSFETs With Scaled ALD $hbox{La}_{2} hbox{O}_{3}/hbox{ZrO}_{2}$ Gate Dielectrics

Publication Year: 2010, Page(s):3295 - 3302
Cited by:  Papers (13)
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Dielectric thin films of La2O3/ZrO2 deposited by atomic layer deposition (ALD) are investigated to be employed in Ge Schottky barrier p-MOSFETs. La2O3 is used as a thin passivation layer and is capped by atomic-layer-deposited ZrO2 as a gate dielectric. As the gate contact TiN capped by W is applied, midgap-level trap densities of ~... View full abstract»

• ### Harmonic Distortion of Unstrained and Strained FinFETs Operating in Saturation

Publication Year: 2010, Page(s):3303 - 3311
Cited by:  Papers (10)
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The harmonic distortion (HD) exhibited by unstrained and biaxially strained fin-shaped field-effect transistors operating in saturation as single-transistor amplifiers has been investigated for devices with different channel lengths L and fin widths Wfin. The study has been performed through device characterization, 3-D device simulations, and modeling. Nonlinearity has be... View full abstract»

• ### Impact of Surface Orientation on the Sensitivity of FinFETs to Process Variations—An Assessment Based on the Analytical Solution of the Schrödinger Equation

Publication Year: 2010, Page(s):3312 - 3317
Cited by:  Papers (1)
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This paper investigates the impact of surface orientation on Vth sensitivity to process variations for Si and Ge fin-shaped field-effect transistors (FinFETs) using an analytical solution of the Schrödinger equation. Our theoretical model considers the parabolic potential well due to short-channel effects and, therefore, can be used to assess the quantum-confinement effec... View full abstract»

• ### Self-Aligned Silicidation of Surround Gate Vertical MOSFETs for Low Cost RF Applications

Publication Year: 2010, Page(s):3318 - 3326
Cited by:  Papers (3)
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We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully integrated with a Fillet Local OXidation (FILOX) process, which thereby delivers low overlap capacitance and high-drive-current vertical devices.... View full abstract»

• ### DC Characteristics of InAlAs/InGaAsSb/InGaAs Double Heterojunction Bipolar Transistors

Publication Year: 2010, Page(s):3327 - 3332
Cited by:  Papers (3)
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DC electrical characteristics of a series of InAlAs/InGaAsSb/InGaAs double heterojunction bipolar transistors (DHBTs) that are grown on InP by molecular beam epitaxy are reported and analyzed. The InGaAsSb base of the transistors leads to a type-I base-emitter junction and a type-II base-collector junction, resulting in unique device characteristics, such as low turn-on voltage, low crossover curr... View full abstract»

• ### Limitations of Field Plate Effect Due to the Silicon Substrate in AlGaN/GaN/AlGaN DHFETs

Publication Year: 2010, Page(s):3333 - 3339
Cited by:  Papers (8)
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We investigated the limitations of the field plate (FP) effect on breakdown voltage VBD that is due to the silicon substrate in AlGaN/GaN/AlGaN double heterostructures field-effect transistors. In our previous work, we showed that in devices with large gate-drain distance (LGD > 8 μm), the breakdown voltage does not linearly increase with L... View full abstract»

• ### Elimination of Current Blocking in Ternary InAlAs-InGaAs-InAlAs Double Heterojunction Bipolar Transistors

Publication Year: 2010, Page(s):3340 - 3347
Cited by:  Papers (7)
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Molecular beam epitaxy-grown wafers are used to fabricate all ternary In0.52Al0.48As-In0.53Ga0.47As-In0.52Al0.48As double heterojunction bipolar transistors (DHBTs) with knee voltages of less than 1 V, showing no current blocking characteristic even at current densities of 200 kA/cm2. A set of wafers with a judicious comb... View full abstract»

• ### Comparison of N- and Ga-Face GaN HEMTs Through Cellular Monte Carlo Simulations

Publication Year: 2010, Page(s):3348 - 3354
Cited by:  Papers (10)
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We compare the performance of GaN HEMT devices based on the established Ga-face technology and the emerging N-face technology. Starting from a state-of-the-art N-face device, we obtain the analogous Ga-face layout imposing the constraint of the same channel charge in both structures, and then, we simulate both the configurations with our full-band cellular Monte Carlo simulator, which includes the... View full abstract»

• ### Processing Techniques for Monolithic Interconnection of Solar Cells at Wafer Level

Publication Year: 2010, Page(s):3355 - 3360
Cited by:  Papers (6)
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Monolithic interconnected modules are large-area high-voltage photovoltaic devices that are realized through solar cell segments that are series-connected via interconnection trenches during wafer processing. This paper investigates different processing techniques, giving detailed information about each processing sequence. In the first approach, a wet chemical etching procedure and photo-defined ... View full abstract»

• ### Characterization of Metamorphic GaAsP/Si Materials and Devices for Photovoltaic Applications

Publication Year: 2010, Page(s):3361 - 3369
Cited by:  Papers (58)
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GaAsyP1-y anion-sublattice compositionally graded buffers and device structures were grown directly on Si(100) substrates by way of a high-quality GaP integration layer, yielding GaAsP target layers having band gaps of photovoltaic interest (1.65-1.8 eV), free of antiphase domains/borders, stacking faults, and microtwins. GaAsyP1-y growths on both ... View full abstract»

• ### Improvement of Reliability of a Flexible Photoluminescent Display Using Organic-Based Materials

Publication Year: 2010, Page(s):3370 - 3376
Cited by:  Papers (11)
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In this paper, a prototype flexible photoluminescent display using organic materials based on a low-temperature process, in which all steps are carried out at under 100 °C, is proposed and fabricated, and the results are compared with those of a conventional plasma display. The proposed flexible photoluminescent display showed a bending radius of about 5 cm, and microplasma was s... View full abstract»

• ### Emission Time Constant of Exoelectron and Formative Delay Time Analyzed by Using Discharge Probability Distribution

Publication Year: 2010, Page(s):3377 - 3387
Cited by:  Papers (3)
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A discharge probability model is proposed to analyze the stochastic distribution of the discharge delay time. The distribution is described as a hybrid function between the exponential and Gaussian distributions and their characteristic properties, such as the emission time constant of an exoelectron and the average and standard deviations of the formative delay time. The calculated results of the... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy