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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 12 • Date Dec. 2010

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Displaying Results 1 - 24 of 24
  • Table of contents

    Publication Year: 2010 , Page(s): C1 - C4
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2010 , Page(s): C2
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  • Computing the Synchronization Regions of Injection-Locked Strongly Nonlinear Oscillators for Frequency Division Applications

    Publication Year: 2010 , Page(s): 1849 - 1857
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (986 KB) |  | HTML iconHTML  

    This paper describes an original method to compute the synchronization regions of injection-locked oscillators that exhibit a strong nonlinear response, such as relaxation or ring architectures. The proposed method is based on the theory of controllably periodically forced oscillators and is implemented within the frame of the time-domain periodic steady-state analysis. The novel method is able to... View full abstract»

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  • Improving FPGA Placement With Dynamically Adaptive Stochastic Tunneling

    Publication Year: 2010 , Page(s): 1858 - 1869
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (616 KB) |  | HTML iconHTML  

    This paper develops a dynamically adaptive stochastic tunneling (DAST) algorithm to avoid the “freezing” problem commonly found when using simulated annealing for circuit placement on field-programmable gate arrays (FPGAs). The main objective is to reduce the placement runtime and improve the quality of final placement. We achieve this by allowing the DAST placer to tunnel energetica... View full abstract»

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  • Improvements on Efficiency and Efficacy of SPFD-Based Rewiring for LUT-Based Circuits

    Publication Year: 2010 , Page(s): 1870 - 1883
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (579 KB) |  | HTML iconHTML  

    This paper proposes two set-of-pairs-of-functions-to-be-distinguished (SPFD)-based rewiring algorithms to be used in a multi-tier rewiring framework, which employs multiple rewiring techniques. The first algorithm has two unique features: 1) a satisfiability problem (SAT) instance was devised so that an unsuccessful rewiring can be identified very quickly, and 2) unlike binary decision diagram-bas... View full abstract»

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  • Efficient Variability-Aware NBTI and Hot Carrier Circuit Reliability Analysis

    Publication Year: 2010 , Page(s): 1884 - 1893
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (585 KB) |  | HTML iconHTML  

    This paper discusses an efficient method to analyze the spatial and temporal reliability of analog and digital circuits. First, a SPICE-based reliability simulator with automatic step-size control is proposed. Both hot carrier degradation and negative bias temperature instability are included in the simulator. Next, a method to analyze the interaction between process variability effects and circui... View full abstract»

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  • Advanced Variance Reduction and Sampling Techniques for Efficient Statistical Timing Analysis

    Publication Year: 2010 , Page(s): 1894 - 1907
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1282 KB) |  | HTML iconHTML  

    The Monte-Carlo (MC) technique is a traditional solution for a reliable statistical analysis, and in contrast to probabilistic methods, it can account for any complicate model. However, a precise analysis that involves a traditional MC-based technique requires many simulation iterations, especially for the extreme quantile points. In this paper, advanced sampling and variance reduction techniques,... View full abstract»

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  • Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs

    Publication Year: 2010 , Page(s): 1908 - 1920
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1431 KB) |  | HTML iconHTML  

    The data retention voltage (DRV) defines the minimum supply voltage for an SRAM cell to hold its state. Intra-die variation causes a statistical distribution of DRV for individual cells in a memory array. We present two fast and accurate methods to estimate the tail of the DRV distribution. The first method uses a new analytical model based on the relationship between DRV and static noise margin. ... View full abstract»

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  • Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers

    Publication Year: 2010 , Page(s): 1921 - 1930
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1575 KB) |  | HTML iconHTML  

    In synchronous circuit designs, clock skew is difficult to minimize because a single physical layout of a clock tree must satisfy multiple constraints in a complicated power mode environment where certain modules may operate with different voltages. In this paper, we use adjustable delay buffers (ADB) whose delays can be tuned or adjusted to minimize clock skew under different power modes. Assumin... View full abstract»

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  • NTHU-Route 2.0: A Robust Global Router for Modern Designs

    Publication Year: 2010 , Page(s): 1931 - 1944
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1305 KB) |  | HTML iconHTML  

    This paper presents a robust global router called NTHU-Route 2.0 that improves the solution quality and runtime of NTHU-Route by the following enhancements: 1) a new history based cost function; 2) new ordering methods for congested region identification and rip-up and reroute; and 3) two implementation techniques. We report convincing experimental results to show the effectiveness of each individ... View full abstract»

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  • MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis

    Publication Year: 2010 , Page(s): 1945 - 1958
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1181 KB) |  | HTML iconHTML  

    Clock mesh networks are well known for their variation tolerance. But their usage is limited to high-end designs due to the significantly high resource requirements compared to clock trees and the lack of automatic mesh synthesis tools. Most existing works on clock mesh networks either deal with semi-custom design or perform optimizations on a given clock mesh. However, the problem of obtaining a ... View full abstract»

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  • Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs

    Publication Year: 2010 , Page(s): 1959 - 1972
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1586 KB) |  | HTML iconHTML  

    3-D integration technology is emerging as an attractive alternative to increase the transistor count for future chips. The majority of the existing 3-D integrated circuit (IC) research is focused on the performance, power, density, and heterogeneous integration benefits offered by 3-D integration. All such advantages, however, ultimately have to translate into cost evaluation when a design strateg... View full abstract»

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  • Buffer Optimization in Network-on-Chip Through Flow Regulation

    Publication Year: 2010 , Page(s): 1973 - 1986
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1754 KB) |  | HTML iconHTML  

    For network-on-chip (NoC) designs, optimizing buffers is an essential task since buffers are a major source of cost and power consumption. This paper proposes flow regulation and has defined a regulation spectrum as a means for system-on-chip architects to control delay and backlog bounds. The regulation is performed per flow for its peak rate and burstiness. However, many flows may have conflicti... View full abstract»

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  • SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips

    Publication Year: 2010 , Page(s): 1987 - 2000
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1714 KB) |  | HTML iconHTML  

    Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient network on chip (NoC) interconnect for a 3-D SoC that meets not only the application performance constraints but also the constraints imposed by the 3-D technology is a significant challenge. In this paper, we present a desig... View full abstract»

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  • An Analytical Approach for Network-on-Chip Performance Analysis

    Publication Year: 2010 , Page(s): 2001 - 2013
    Cited by:  Papers (25)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1451 KB) |  | HTML iconHTML  

    Networks-on-chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters affect the actual network performance. Therefore, it is practically impossible to use simulation for op... View full abstract»

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  • An Advanced BIRA for Memories With an Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer

    Publication Year: 2010 , Page(s): 2014 - 2026
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2035 KB) |  | HTML iconHTML  

    As memory capacity and density grow, a corresponding increase in the number of defects decreases the yield and quality of embedded memories for systems-on-chip as well as commodity memories. For embedded memories, built-in redundancy analysis (BIRA) is widely used to solve quality and yield issues by replacing faulty cells with healthy redundant cells. Many BIRA approaches require extra hardware o... View full abstract»

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  • A Novel SAT-Based Approach to the Task Graph Cost-Optimal Scheduling Problem

    Publication Year: 2010 , Page(s): 2027 - 2040
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1014 KB) |  | HTML iconHTML  

    The task graph cost-optimal scheduling problem consists in scheduling a certain number of interdependent tasks onto a set of heterogeneous processors (characterized by idle and running rates per time unit), minimizing the cost of the entire process. This paper provides a novel formulation for this scheduling puzzle, in which an optimal solution is computed through a sequence of binate covering pro... View full abstract»

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  • Topology Synthesis for Low Power Cascaded Crossbar Switches

    Publication Year: 2010 , Page(s): 2041 - 2045
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (306 KB) |  | HTML iconHTML  

    Crossbar switch network has an increasing impact on such critical measures as throughput, latency, area, and power consumption of complex system-on-chip as technology scales to deep submicrometer. With high clock frequency crossbar switch network design, global wire delay and pipeline registers inserted for throughput are important because they affect area, frequency, and power consumption of the ... View full abstract»

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  • Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style

    Publication Year: 2010 , Page(s): 2046 - 2050
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (728 KB) |  | HTML iconHTML  

    In recent years, structured application-specific integrated circuit (ASIC) design style has lessened the importance of mask cost. Multiple structured ASIC chip designs share the same pre-fabricated device and wire masks. Nevertheless, the interconnection delay in a pre-fabricated wire slows down circuit performance as a result of high capacitive load. We propose a dual-rail routing architecture th... View full abstract»

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  • DiSC: A New Diagnosis Method for Multiple Scan Chain Failures

    Publication Year: 2010 , Page(s): 2051 - 2055
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (502 KB) |  | HTML iconHTML  

    In scan-based testing environments, identifying the scan chain failures can be of significant help in guiding the failure analysis process for yield improvement. In this paper, we propose an efficient scan chain diagnosis method using a symbolic fault simulation to achieve high diagnostic resolution and small candidate list for single and multiple defects in scan chains. The main ideas of the prop... View full abstract»

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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2010 , Page(s): 2056
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    Freely Available from IEEE
  • 2010 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 29

    Publication Year: 2010 , Page(s): 2057 - 2078
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    Freely Available from IEEE
  • 2011 IEEE membership form

    Publication Year: 2010 , Page(s): 2079 - 2080
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    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2010 , Page(s): C3
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    Freely Available from IEEE

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu