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Electron Device Letters, IEEE

Issue 5 • Date May 1993

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Displaying Results 1 - 19 of 19
  • On the electrical conduction in the interpolysilicon dielectric layers

    Publication Year: 1993 , Page(s): 213 - 215
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (310 KB)  

    To reduce the low-field electrical conductivity of interpolysilicon dielectrics used in electrically erasable programmable read-only (EEPROM) memories devices, the roughness of the poly-SiO/sub 2/ interface until now has been decreased in two ways: (1) by increasing the temperature of oxidation and doping of polysilicon combined with low-pressure chemical vapor deposition (LPCVD) of silicon (undoped or in-situ doped) in the amorphous phase, or (2) by the use of LPCVD high-temperature oxide (HTO) deposited over polycrystalline silicon. The advantages of both methods are combined, and electrical conduction results for an interpoly structure based on LPCVD smooth surface polysilicon and LPCVD HTO SiO/sub 2/ are presented. The data are interpreted in terms of the Fowler-Nordheim mechanism.<> View full abstract»

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  • Highly reliable, high-C DRAM storage capacitors with CVD TA/sub 2/O/sub 5/ films on rugged polysilicon

    Publication Year: 1993 , Page(s): 216 - 218
    Cited by:  Papers (7)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (301 KB)  

    The authors report on a highly reliable stacked storage capacitor with ultrahigh capacitance using rapid-thermal-annealed low-pressure chemical vapor deposited (LPCVD) Ta/sub 2/O/sub 5/ films ( approximately 100 AA) deposited on NH/sub 3/-nitrided rugged poly-Si electrodes. Capacitances as high as 20.4 fF/ mu /sup 2/ (corresponding to the thinnest t/sub ox.eff/ (16.9 AA) ever reported using LPCVD-Ta/sub 2/O/sub 5/ and poly-Si technologies) have been achieved with excellent leakage current and time-dependent dielectric breakdown (TDDB) characteristics. Extensive electrical characterization over a wide temperature range ( approximately 25-300 degrees C) shows that Ta/sub 2/O/sub 5/ films on rugged poly-Si electrodes have a better temperature stability in dielectric leakage and breakdown compared to the films on smooth poly-Si electrodes.<> View full abstract»

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  • MICROX-an all-silicon technology for monolithic microwave integrated circuits

    Publication Year: 1993 , Page(s): 219 - 221
    Cited by:  Papers (33)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (278 KB)  

    An improved silicon-on-insulator (SOI) approach offers devices and circuits operating to 10 GHz by providing formerly unattainable capabilities in bulk silicon: reduced junction-to-substrate capacitances in FETs and bipolar transistors, inherent electrical isolation between devices, and low-loss microstrip lines. The concept, called MICROX (patent pending), is based on the SIMOX process, but uses very-high-resistivity (typically>10000 Omega -cm) silicon substrates, MICROX NMOS transistors of effective gate length 0.25 mu m give a maximum frequency of operation, f/sub max/, of 32 GHz and f/sub T/ of 23.6 GHz in large-periphery (4 mu m*50 mu m) devices with no correction for the parasitic effects of the pads. The measured minimum noise figure is 1.5 dB at 2 GHz with associated gain of 17.5 dB, an improvement over previously reported values for silicon FETs.<> View full abstract»

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  • Characteristics of MOS capacitors of BF/sub 2/ or B implanted polysilicon gate with and without POCl/sub 3/ co-doped

    Publication Year: 1993 , Page(s): 222 - 224
    Cited by:  Papers (4)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (271 KB)  

    The characteristics of BF/sub 2/- or B-implanted polysilicon gate MOS capacitors with and without POCl/sub 3/ codoped were studied. It was found that the gate oxide thickness was increased very significantly with the number of high-temperature thermal cycles for BF/sub 2/-implanted polysilicon MOS capacitors, but this was not true for POCl/sub 3/-codoped polysilicon MOS capacitors. A model that interprets this phenomenon well was developed using the results of SIMS (secondary ion ion mass spectrometry) measurements.<> View full abstract»

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  • Degradation of N/sub 2/O-annealed MOSFET characteristics in response to dynamic oxide stressing

    Publication Year: 1993 , Page(s): 225 - 227
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (259 KB)  

    The performance of n-MOSFETs with furnace N/sub 2/O-annealed gate oxides under dynamic Fowler-Nordheim bipolar stress was studied and compared with that of conventional oxide (OX). Time-dependent dielectric breakdown at high frequency was shown to be improved for the N/sub 2/O-annealed devices compared with that for devices with OX. In addition, a smaller V/sub t/ shift after stress was found for nitrided samples. The shift decreased with increasing stressing frequency and annealing temperature. Measurements of both G/sub m/ and D/sub it/ revealed a peak frequency at which the degradation was the worst. A hole trapping/migration model has been proposed to explain this.<> View full abstract»

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  • A physical model for the gate current injection in p-channel MOSFET's

    Publication Year: 1993 , Page(s): 228 - 230
    Cited by:  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB)  

    A quantitative physical model for calculating the hot-electron injection probability, I/sub G//I/sub SUB/, for both buried and surface p-channel MOSFETs is presented. The model utilizes the two-dimensional potential contours generated by PISCES, and integrates the probability of substrate hot-electron injection across the high-field region near the drain. The known phenomenon that buried-channel (BC) PMOS has higher hot-electron injection probability but lower channel field (I/sub SUB//I/sub D/) than a similar surface-channel (SC) device is successfully modeled. This phenomenon can be attributed to the larger energy band hump-up near the drain and the larger oxide field (and thus greater barrier lowering) at a given bias condition for the buried-channel device. The I/sub G/ characteristics can be obtained from the calculated I/sub G//I/sub SUB/ ratio, using readily available I/sub SUB/ values.<> View full abstract»

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  • High-field-induced leakage in ultrathin N/sub 2/O oxides

    Publication Year: 1993 , Page(s): 231 - 233
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB)  

    Stress-induced leakage current (SILC) is studied in ultrathin ( approximately 50 AA) gate oxides grown in N/sub 2/O or O/sub 2/ ambient, using rapid thermal processing (N/sub 2/O oxide or control oxide, respectively). MOS capacitors with N/sub 2/O oxides exhibit much suppressed SILC compared to the control oxide for successive ramp-up, constant voltage DC, and AC (bipolar and unipolar) stresses. The mechanism for SILC is discussed, and the suppressed SILC in N/sub 2/O oxide is attributed to suppressed interface state generation due to nitrogen incorporation at the Si/SUO/sub 2/ interface during N/sub 2/O oxidation.<> View full abstract»

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  • Bipolar-FET hybrid-mode operation of quarter-micrometer SOI MOSFETs (MESFETs read MOSFETs)

    Publication Year: 1993 , Page(s): 234 - 236
    Cited by:  Papers (30)  |  Patents (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (259 KB)  

    A hybrid mode of device operation, in which both bipolar and MOSFET currents flow simultaneously, has been experimentally investigated using quarter-micrometer-channel-length MOSFET's which were fabricated on SIMOX silicon-on-insulator substrates. This mode of device operation is achieved by connecting the gate of a non-fully-depleted SOI MOSFET to the edges of its floating body. Both the maximum G/sub m/ and current drive at 1.5* higher than the MOSFET's normal mode. Bipolar-junction-transistor (BJT)-like 60-mV/decade turn-off behavior is also achieved. This mode of operation is very promising for low-voltage, low-power, very-high-speed logic as well as for on-chip analog functions.<> View full abstract»

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  • The improvement of short-channel effects due to oxidation-induced boron redistribution for counter-implantation p-MOSFET's

    Publication Year: 1993 , Page(s): 237 - 239
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB)  

    Delayed appearance of short-channel effects in the threshold voltage falloff has been observed for counterimplantation p-MOSFETs. The phenomenon is attributed to the oxidation-induced boron redistribution along the channel. SUPREM-3 and MINIMOS-5 and the Orlowski method were used to quantitatively characterize this behavior. Quite good agreement between simulation and experimental data were obtained. It was found that the device characteristics of submicrometer counterimplanted p-MOSFETs are improved due to the effects of boron redistribution near the channel edge.<> View full abstract»

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  • On the pseudo-subthreshold characteristics of polycrystalline-silicon thin-film transistors with large grain size

    Publication Year: 1993 , Page(s): 240 - 242
    Cited by:  Papers (27)  |  Patents (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (285 KB)  

    A two-dimensional nonplanar device simulator for polycrystalline-silicon thin-film transistors (poly-Si TFTs) was developed, in which the influence of trapped charges and carrier scattering within the grain boundary region are incorporated into Poisson's equations and drift-diffusion current formulations, respectively. With this simulator, the I-V characteristics of poly-Si TFT devices can be characterized. TFTs in polycrystalline silicon were fabricated to test the simulator. Special attention was paid to the conduction mechanism in poly-Si TFTs with large grain size. A concept called the pseudo-subthreshold region is presented to explain the observed behavior. The key factors affecting the pseudosubthreshold slope were investigated and elucidated using the simulator.<> View full abstract»

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  • Decrease of gate oxide dielectric constant in tungsten polycide gate processes

    Publication Year: 1993 , Page(s): 243 - 245
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    The gate oxide thickness for tungsten (W) polycide gate processes is studied, with tungsten silicide (WSi/sub x/) deposited either by chemical vapor deposition (CVD) or sputtering. For WSi/sub x/ deposited by CVD, it is found that the effective thickness of gate oxide as determined by CV measurement increases in all cases if the annealing temperature is 900 degrees C or higher. However, high-resolution transmission electron microscopy (TEM) measurement indicates that the physical thickness does not change after a 900 degrees C anneal. In this case, the dielectric constant of the gate oxide decreases by 7%. As the annealing temperature increases to 1000 degrees C, CV and TEM measurements give the same thickness and the decrease of the dielectric constant disappears. In contrast, for WSi/sub x/ film deposited by sputtering, annealing at 900 degrees C has no effect on the gate oxide thickness as measured by CV and TEM.<> View full abstract»

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  • Large suspended inductors on silicon and their use in a 2- mu m CMOS RF amplifier

    Publication Year: 1993 , Page(s): 246 - 248
    Cited by:  Papers (229)  |  Patents (83)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (265 KB)  

    Large spiral inductors encased in oxide over silicon are shown to operate beyond the UHF band when the capacitance and loss resistance are greatly reduced by selective removal of the underlying substrate. Using a 100-nH inductor whose self-resonance lies at 3 GHz, a balanced tuned amplifier with a gain of 14 dB centered at 770 MHz has been implemented in a standard digital 2- mu m CMOS IC process. The core amplifier noise figure is 6 dB, and the power dissipation is 7 mW for a 3-V supply.<> View full abstract»

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  • Electromigration characteristics of copper interconnects

    Publication Year: 1993 , Page(s): 249 - 251
    Cited by:  Papers (20)  |  Patents (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (250 KB)  

    The electromigration characteristics of electroless plated copper interconnects have been investigated under DC and time-varying current stressing. A scheme for selected electroless Cu plating by using 150-AA Co as the seeding layer is reported. The Cu DC and pulse-DC lifetimes are found to be one and two orders of magnitude longer than that of Al-4% Cu/TiW and Al-2% Si interconnects at 275 degrees C, and the extracted Cu lifetime at 75 degrees C is about three and five orders of magnitude longer than that of Al-4% Cu/TiW and Al-2% Si, respectively. As previously reported for Al metallization, the Cu bipolar lifetimes were found to be orders of magnitude longer than their DC lifetimes under the same peak stressing current density because of the partial recovery of electromigration damage during the opposing phases of bipolar stressing.<> View full abstract»

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  • Resolving the mechanisms of current gain increase under forward current stress in poly emitter n-p-n transistors

    Publication Year: 1993 , Page(s): 252 - 255
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (347 KB)  

    The mechanisms behind moderate bias current gain ( beta ) increase of n-p-n transistors under forward current stress are investigated in polysilicon emitter transistors processed with different dopant impurities and concentrations, and with different amounts of hydrogen plasma treatment. The results suggest that transport of atomic hydrogen toward the poly/monosilicon interface region and its subsequent passivation of dangling bonds at both poly grain boundaries and the poly/monosilicon interface are responsible for the moderate bias beta increase. To alleviate the beta instability, elimination of hydrogen involvement and/or a higher doping concentration inside the poly emitter in the back-end-of-line (BEOL) processes are/is recommended.<> View full abstract»

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  • 1/f noise in hot-carrier damaged MOSFET's: effects of oxide charge and interface traps

    Publication Year: 1993 , Page(s): 256 - 258
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (255 KB)  

    The 1/f noise in the drain current of hot-carrier damaged MOSFETs biased in weak inversion has been studied. By the use of a biased annealing treatment to simultaneously decrease the density of oxide trapped charge (N/sub ot/) and increase the density of interface traps (D/sub it/), the authors have separated the contributions of these two kinds of defects. The results clearly indicate that, while the low-frequency 1/f noise is correlated with N/sub ot/, the high-frequency 1/f noise is correlated with D/sub it/.<> View full abstract»

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  • InGaAs/InAlAs HEMT with a strained InGaP Schottky contact layer

    Publication Year: 1993 , Page(s): 259 - 261
    Cited by:  Papers (10)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    The authors have fabricated an InGaAs/InAlAs HEMT structure with a strained InGaP Schottky contact layer to achieve selective wet gate recess etching and to improve reliability for thermal stress. Strained In/sub 0.75/Ga/sub 0.25/P grown on InAlAs has been revealed to have sufficient Schottky barrier height for use as a gate contact. Threshold voltage standard deviation has been reduced to one fifth that of a conventional InGaAs/InAlAs HEMT, as a result of successful selective recess etching. After thermal treatment at 300 degrees C for 5 min, the drain current and transconductance did not change, while those of the conventional HEMT decreased by more than 10%.<> View full abstract»

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  • Gate current injection in MOSFET's with a split-gate (virtual drain) structure

    Publication Year: 1993 , Page(s): 262 - 264
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (290 KB)  

    Gate current injection into the gate oxide of MOSFETs with a split-gate (virtual drain) structure is examined. The split-gate structure is commonly encountered in flash EEPROM and CCDs. An important parameter characterizing the gate current injection is the ratio phi /sub b// phi /sub i/ (where phi /sub b/ is the effective energy barrier for electron injection into gate oxide, and phi /sub i/, is the impact ionization energy). Measurements of phi /sub b// phi /sub i/ at relatively constant vertical and lateral electric fields are reported. Through the use of a novel triple-gate MOSFET, the drain current as well as the lateral and vertical electric field at the point of injection were independently controlled during the measurements. The measured phi /sub b// phi /sub i/ showed a dependence on gate and drain biases not reported previously.<> View full abstract»

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  • Effects of residual surface nitrogen on the dielectric breakdown characteristics of regrown oxides

    Publication Year: 1993 , Page(s): 265 - 267
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB)  

    Effects of residual surface nitrogen, remaining on the Si surface after stripping off tunneling oxynitrides (N/sub 2/O-grown or NH/sub 3/-nitrided oxides), on the quality of the regrown gate oxides are studied. Residual surface nitrogen is observed to reduce the breakdown field and degrade the time-dependent dielectric breakdown (TDDB) characteristics of the subsequently grown gate oxides. Results show that oxide regrowth in N/sub 2/O, rather than O/sub 2/, can significantly suppress these undesirable effects.<> View full abstract»

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  • Temperature dependence of MOSFET substrate current

    Publication Year: 1993 , Page(s): 268 - 271
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (321 KB)  

    Hitherto, theoretical models for MOSFET substrate current predicted that substrate current is a strong function of temperature. However, experimental data presented in this and previous studies show that the ratio of substrate current to drain current is insensitive to temperature over the range 77 to 300 K. The authors propose a modified model for an electron mean-free path (MFP) in the substrate current based on the concept of energy relaxation. The different between the energy and momentum relaxation MFP is clarified, and it is shown that a substrate current model with modified MFP can explain the temperature dependence of the substrate current.<> View full abstract»

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