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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 3 • Date Mar 1993

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Displaying Results 1 - 6 of 6
  • A computationally efficient unified approach to the numerical analysis of the sensitivity and noise of semiconductor devices

    Publication Year: 1993 , Page(s): 425 - 438
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1252 KB)  

    The authors present a computationally efficient unified approach to the numerical simulation of sensitivity and noise in majority-carrier semiconductor devices that is based on the extension to device simulation of the adjoint method for sensitivity and noise analysis of electrical networks. Sensitivity and device noise analysis based on physical models are shown to have a common background, since they amount to evaluating the small-signal device response to an impressed, distributed current source. This problem is addressed by means of a Green's function technique akin to Shockley's impedance field method. To allow the efficient numerical evaluation of the Green's function within the framework of a discretized physical model, inter-reciprocity concepts, based on the introduction of an adjoint device, are exploited. Examples of implementation involving GaAs MESFETs are discussed View full abstract»

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  • Universal MOSFET hole mobility degradation models for circuit simulation

    Publication Year: 1993 , Page(s): 439 - 445
    Cited by:  Papers (5)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (612 KB)  

    Universal, semi-empirical MOSFET hole inversion layer mobility degradation models for use in circuit simulation programs such as SPICE are presented. By accurately predicting the mobility degradation due to acoustic phonon scattering and surface roughness scattering for p-channel MOSFETs at room temperature, these models eliminate the need for fitting parameters for each technology, which is required in the current SPICE level 3 model. The expressions reported accurately predict the mobility over a very wide range of channel doping concentrations, gate oxide thicknesses, gate voltage, and substrate bias, and they agree very well with recently published experimental mobility degradation data. When implemented in a circuit simulation code, these models will accurately determine the channel mobility in surface p-channel MOSFETs using only the channel doping concentration, gate oxide thickness, substate bias, and applied gate drive voltage as input parameters View full abstract»

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  • Don't care set specifications in combinational and synchronous logic circuits

    Publication Year: 1993 , Page(s): 365 - 388
    Cited by:  Papers (21)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1848 KB)  

    A unified framework for the specification and computation of don't care conditions for combinational and synchronous multiple-level digital circuits is presented. Circuits are characterized in terms of graphs, logic functions and don't care conditions induced by the external and internal interconnections. The replacement of a gate in a synchronous logic network is modeled by a perturbation of the corresponding logic function, and it is shown that the don't care conditions for the gate optimization represent the bound on this perturbation. Algorithms to compute such don't care conditions in both the combinational and synchronous case are presented. The implementation of the algorithms and the experimental results are discussed View full abstract»

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  • VLSI logic and fault simulation on general-purpose parallel computers

    Publication Year: 1993 , Page(s): 446 - 460
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1256 KB)  

    The authors define a general framework for the parallel simulation of digital systems and develop and evaluate tools for logic and fault simulation that have a good cost-performance ratio. They first review previous work and identify central issues. Then a high-level process model of parallel simulation is presented to clarify essential design choices. Algorithms for parallel logic and fault simulation of synchronous gate-level designs are introduced. The algorithms are based on a partitioning approach that reduces the number of necessary synchronizations between processors. A simple performance model characterizes the dependence on some crucial parameters. Experimental results for some large benchmarks are given, using prototype implementations for both message-passing and shared-memory machines View full abstract»

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  • Applying simulated evolution to high level synthesis

    Publication Year: 1993 , Page(s): 389 - 409
    Cited by:  Papers (22)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1900 KB)  

    A general optimization algorithm known as simulated evolution (SE) is applied to the tasks of scheduling and allocation in high level synthesis. Basically, SE-based synthesis explores the design space by repeatedly ripping up parts of a design in a probabilistic manner and reconstructing them using application-specific heuristics that combine rapid design iterations and probabilistic hill climbing to achieve effective design space exploration. Benchmark results are presented to demonstrate the effectiveness of this approach. The results of a number of experiments that provide insight into why SE-based synthesis works so well are given View full abstract»

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  • An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis

    Publication Year: 1993 , Page(s): 410 - 424
    Cited by:  Papers (13)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1516 KB)  

    A layout style that enables either an automatic layout synthesizer or a layout designer to take full advantage of the second metal layer available from today's technology is proposed. The style not only facilitates power/ground diffusion overlapping but also simplifies the intracell routing problem by having power/ground in the middle and routing in the upper and the lower constraint-free regions. An automatic leaf cell layout synthesizer, called THEDA.P, that is based on the proposed style has been implement. Using the same transistor placement algorithm, THEDA.P outperforms a synthesizer based on T. Uehara and W.M. van Cleemput's (1981) approach by almost 20% in layout compactness across a wide range of small-scale integrated circuits. THEDA.P has been used to build a standard cell library that was previously handcrafted. Results from designing two modules show that THEDA.P's layout quality is very competitive View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu