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Electron Devices, IEEE Transactions on

Issue 11 • Date Nov. 2010

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Displaying Results 1 - 25 of 60
  • Table of contents

    Page(s): C1 - 2782
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  • IEEE Transactions on Electron Devices publication information

    Page(s): C2
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  • Changes in the Editorial Board

    Page(s): 2783 - 2784
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  • FinFET SRAM Optimization With Fin Thickness and Surface Orientation

    Page(s): 2785 - 2793
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1116 KB) |  | HTML iconHTML  

    In this paper, the design space, including fin thickness (Tfin), fin height (Hfin), fin ratio of bit-cell transistors, and surface orientation, is researched to optimize the stability, leakage current, array dynamic energy, and read/write delay of the FinFET SRAM under layout area constraints. The simulation results, which consider the variations of both Tfin and threshold voltage (Vth), show that most FinFET SRAM configurations achieve a superior read/write noise margin when compared with planar SRAMs. However, when two fins are used as pass gate transistors (PG) in FinFET SRAMs, enormous array dynamic energy is required due to the increased effective gate and drain capacitance. On the other hand, a FinFET SRAM with a one-fin PG in the (110) plane shows a smaller write noise margin than the planar SRAM. Thus, the one-fin PG in the (100) plane is suitable for FinFET SRAM design. The one-fin PG FinFET SRAM with Tfin = 10 nm and Hfin = 40 nm in the (100) plane achieves a three times larger noise margin when compared with the planar SRAM and consumes a 17% smaller bit-line toggling array energy at a cost of a 22% larger word-line toggling energy. It also achieves a 2.3 times smaller read delay and a 30% smaller write delay when compared with the planar SRAM. View full abstract»

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  • Modified Potential Well Formed by \hbox {Si/SiO}_{2}/ \hbox {TiN/TiO}_{2}/\hbox {SiO}_{2}/\hbox {TaN} for Flash Memory Application

    Page(s): 2794 - 2800
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (447 KB) |  | HTML iconHTML  

    This paper proposes a modified engineered-potentialwell (MW) for NAND flash memory application. The MW was formed by using a transitional SiO2/SiOx,Na-TiOx,Ny tunnel barrier, a trap-rich TiO2 trapping layer, and an abrupt SiO2 block barrier. The transitional tunnel barrier shrinks to enhance the tunneling of carriers during programming/erasing (P/E) and extends to suppress charge loss during data retention. Deep-level transient spectroscopy suggests that this tunnel barrier has few shallow traps after a N2 + O2 thermal treatment, and the TiO2 trapping layer has deep electron traps. With the variable tunnel barrier and deep electron traps, the MW device showed promising performance in fast programming (<; μs) at low-voltage operation (7-10 MV/cm), good P/E endurance (> 106 P/E cycles), large threshold voltage window (ΔVth =M> V), as well as improved data retention at 125 °C. View full abstract»

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  • Understanding LER-Induced MOSFET V_{T} Variability—Part I: Three-Dimensional Simulation of Large Statistical Samples

    Page(s): 2801 - 2807
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    In this paper, using computationally intensive 3-D simulations in a grid computing environment, we perform a detailed study of line-edge-roughness (LER)-induced threshold voltage variability in contemporary MOSFETs. Statistical ensembles of tens of thousands transistors have been simulated. Our analysis has been predominantly performed on a 35-nm channel-length bulk MOSFET test bed, widely used in previous studies to investigate the impact of different statistical variability sources. Comprehensive data mining and statistical analysis provide information about the shape of the distribution of the device threshold voltage, which is significantly non-Gaussian. Strong nonlinear correlation has been observed between the threshold voltage and the average channel length of the simulated devices. The width dependence of LER-induced threshold voltage variability has also been simulated and analyzed. Additional confirmation of the basic conclusions from the simulation and statistical analysis of the 35-nm test bed transistor is provided by the simulation of a 42-nm physical channel-length bulk LP MOSFET, a 32-nm channel-length thin-body silicon-on-insulator (SOI) MOSFET, and a 22-nm channel-length double-gate (DG) MOSFET. View full abstract»

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  • Understanding LER-Induced MOSFET V_{T} Variability—Part II: Reconstructing the Distribution

    Page(s): 2808 - 2813
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (702 KB) |  | HTML iconHTML  

    In this paper, we examine, in more detail, the strong correlation between the distribution of threshold voltage (VT) and the average channel length (C̅) discovered in Part I of this paper. Based on the results of statistical analysis, we investigate an approach whereby the line-edge-roughness (LER)-induced distribution of VT can be reconstructed based on the convolution of the distribution of (C̅) and the subdistributions of VT at particular values of (C̅). Further analysis demonstrates that the actual shape of the subdistributions has little impact on the accuracy of the reconstruction. This result allows a fast and economical semianalytical approach for the simulation of LER-induced VT variability, based on the nonlinear transformation of the distribution of (C̅) into the distribution of VT using the channel length dependence of the threshold voltage as a mapping function. The accuracy of the semianalytical approach has been confirmed by comparison with the distributions of VT obtained for a broad range of conventional and novel MOSFETs using comprehensive 3-D simulations. View full abstract»

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  • Characterization of Inversion-Layer Capacitance of Electrons in High- k /Metal Gate Stacks

    Page(s): 2814 - 2820
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB) |  | HTML iconHTML  

    The inversion-layer capacitance Cinv of electrons in high-k/metal gate stacks (HKMGs) is studied theoretically and experimentally from the viewpoint of the penetration of electrons into the dielectrics. The numerical calculation of Cinv in the dielectric/substrate bilayer structure has clarified the influence of penetration on Cinv . Cinv in an HKMG is evaluated experimentally and is compared with the computational predictions in terms of the dependence on the dielectric boundary and the silicon crystal orientation. The consistency of the experiment and the calculation is the first evidence for the considerable modulation of Cinv due to penetration in the actual HKMG. Moreover, the dependence of Cinv on substrate biasing is investigated. The detailed analysis of Cinv in the system where the confinement of the inversion layer is intentionally changed has led to a further understanding of Cinv determined by penetration. View full abstract»

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  • Total Performance of 32-nm-Node Ultralow- k /Cu Dual-Damascene Interconnects Featuring Short-TAT Silylated Porous Silica (k = \hbox {2.1})

    Page(s): 2821 - 2830
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    The total performance of low-k/Cu interconnects featuring short turnaround-time (TAT) silylated scalable porous silica (Po-SiO, k = 2.1) with high porosity (50%) is demonstrated. The TAT for the film formation process including silylation treatment is about 25% reduced by adding a promoter, causing reinforcement of the film. Applying this improved Po-SiO, a 140-nm-pitch dual-damascene structure is successfully achieved. The wiring capacitance showed 10% reduction, compared to the conventional porous SiOC (ULK, k = 2.65). Sufficient interconnect reliability and packaging characteristics for the circuit-under-pad structure are also obtained. The predicted circuit performance was 8% higher than ULK in the 32-nm node. View full abstract»

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  • Determination of the Base-Dopant Concentration of Large-Area Crystalline Silicon Solar Cells

    Page(s): 2831 - 2837
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (630 KB) |  | HTML iconHTML  

    The capacitance-voltage (CV) measurement is a precise and fast method to determine base-dopant concentrations of crystalline silicon solar cells. Since available measurement equipment is usually limited in its current output, the application of CV analysis has been limited to small-area solar cells in research laboratories. We present an experimental setup that is capable of measuring CV curves with a current output of up to 2 A. Using this setup, we demonstrate the applicability of CV measurements to large-area industrial solar cells for base-dopant concentrations ranging between 6.0 × 1014 cm-3 and 4.2 &times;1016 cm-3. An area enhancement factor f quantifying the relation between the macroscopic cell area and the active junction area is determined for alkaline textured mono- and isotextured multicrystalline silicon solar cells. Comparing the base dopant of the CV analysis with four-point probe measurements, we achieve an agreement with an uncertainty of 10%. For alkaline textured monocrystalline silicon solar cells, we demonstrate that the area enhancement factor can be extracted from the ratio of the pyramid base length and emitter thickness. View full abstract»

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  • Thermal Circuit for SOI MOSFET Structure Accounting for Nonisothermal Effects

    Page(s): 2838 - 2847
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (693 KB) |  | HTML iconHTML  

    An accurate thermal circuit model for 2-D silicon-on-insulator (SOI) MOSFETs is presented to account for nonisothermal effects. The circuit model is modified from an approach developed earlier for the temperature distribution in 2-D SOI MOSFETs. A generalized approach to establishing a nonisothermal circuit and its circuit elements is presented for different SOI structures, such as multidevices on a single island and multifinger structure. The developed circuit model is verified with the finite-element method (FEM) in different SOI structures, including a structure coupled with interconnects. Heat flow to the contacts, poly gate, and buried oxide (BOX)/field oxide (FOX) is examined. Heat exchange via FOX between neighboring islands is carefully investigated, as compared to the FEM. It is shown from the developed model and FEM simulations that heat exchange via FOX between two thin islands is negligible if the distance between the islands is near or greater than the island thickness plus the BOX thickness. View full abstract»

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  • FinFET Mismatch in Subthreshold Region: Theory and Experiments

    Page(s): 2848 - 2856
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (390 KB) |  | HTML iconHTML  

    In this paper, we study the drain-current mismatch of FinFETs in subthreshold, from both modeling and experimental point of view. We propose a simple model that takes into account the effect of threshold voltage and subthreshold swing fluctuations and their correlation. For long-channel devices (longer than a critical length LC), characterized by a subthreshold swing close to the ideal value, the overall current mismatch is dominated by threshold voltage fluctuations and, therefore, is gate voltage independent. The subthreshold swing fluctuations give a negligible effect on the drain-current mismatch and are uncorrelated with the threshold voltage fluctuations. For short-channel devices (shorter than a critical length LC), characterized by a strong dependence of subthreshold swing on the channel length, the overall current mismatch presents an additional relevant contribution associated with the subthreshold swing fluctuations. This component depends on the gate voltage overdrive and is ascribed to the gate line edge roughness, resulting in a partial correlation between threshold voltage and subthreshold swing fluctuations. View full abstract»

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  • Very High Room-Temperature Peak-to-Valley Current Ratio in Si Esaki Tunneling Diodes (March 2010)

    Page(s): 2857 - 2863
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (562 KB) |  | HTML iconHTML  

    Current density-voltage characteristics of Si p+ -i-n+ Esaki tunneling diodes are presented, which are grown with low-temperature molecular beam epitaxy. The Esaki structures are realized without a postgrowth annealing step. A maximum peak-to-valley current ratio of more than 5 was obtained at room temperature. To the authors' knowledge, this result is the highest reported value for any pure Si tunnel diode. A temperature study of the current density-voltage characteristics separates all three forward current density components: 1) interband tunneling current density; 2) excess current density through defect-assisted tunneling; and 3) diffusion current density. The results show the high potential for the future development of Si Esaki tunneling diodes and predict an increase of the peak-to-valley current ratio up to 15 if the excess current density is suppressed. View full abstract»

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  • Investigation of Nanowire Line-Edge Roughness in Gate-All-Around Silicon Nanowire MOSFETs

    Page(s): 2864 - 2871
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1025 KB) |  | HTML iconHTML  

    In this paper, the effects of nanowire line-edge roughness (LER) in gate-all-around silicon nanowire MOSFETs (SNWTs) are comprehensively investigated through 3-D statistical simulation. The LER impacts on both the device performance variation and mean value degradation are discussed in detail. Due to the unique nature of a nanowire structure, the LER in SNWTs contains two degrees of freedom, which allows the nanowire edges to vary in arbitrary transverse direction and which is different from the LER in traditional devices with one degree of freedom. In order to identify the relative importance of the diameter and center position variations, the nanowire LER can be considered as the combination of two basic types: One has a varied diameter with a fixed center (type A), and the other has a varied center position with a fixed diameter (type B). The results indicate the tradeoff between these two types of LER, with type A of a larger performance variation and type B of a larger performance degradation. Furthermore, as the gate length Lg shrinks below the correlation length Λ of the nanowire LER, the impacts from the source/drain extension region will dominate the variation. The impact of the main LER parameters is discussed for the scaled case with a non-Gaussian distribution in the device electrical parameters observed, and a new statistical method is proposed for better evaluation. On the other hand, the performance variation becomes insensitive to the correlation length in the case of Λ > Lg, which indicates a higher tolerance for the nanowire LER design in ultrascaled SNWTs. The optimized LER parameters are also given for the nanowire LER design with acceptable performance variation and suppressed mean value degradation in SNWTs. View full abstract»

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  • Understanding of High-Throughput Rapid Thermal Firing of Screen-Printed Contacts to Large-Area Cast Multicrystalline Si Solar Cells

    Page(s): 2872 - 2879
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (573 KB) |  | HTML iconHTML  

    In this paper, we investigate the conditions that are necessary to produce high-quality screen-printed metal contacts to large-area cast multicrystalline Si solar cells using a high-throughput infrared conveyer belt furnace. We show that high sinter ramp rates produce a back-surface recombination velocity of ~400 cm/s and the most homogeneous Al back-surface field. We also show that the short sinter dwell time produces a thin Ag/Si interfacial glass layer; optimal bulk defect hydrogenation, as indicated by final bulk lifetime improvements; and low Ag specific contact resistance. The fundamental research and understanding applied here produces high fill factors, low series resistance, and high efficiency. View full abstract»

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  • Electronic Properties and Orientation-Dependent Performance of InAs Nanowire Transistors

    Page(s): 2880 - 2885
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (455 KB) |  | HTML iconHTML  

    The electronic properties, namely, the band structures, the band gaps, and the electron effective masses of hydrogen-passivated InAs nanowires grown in 〈100〉 , 〈110〉, and 〈111〉 crystallographic directions are studied using sp3d5s* orbital-basis tight-binding model. We then parameterize the band gaps and electron effective masses to facilitate device simulation and to study the orientation-dependent performance of n-channel InAs nanowire transistors using a top-of-the-barrier model. The 〈111〉 and 〈110〉 wire transistors have better performance metrics. The quantum-confinement effect is largest in the 〈100〉 wire, which results in a higher band gap and a heavier effective mass for relatively smaller diameter wires. The consequence is lower current, higher density of states, higher quantum capacitance, and longer delay in the 〈100〉 wire transistors. The 〈110〉 and 〈111〉 wires have a very similar quantum-confinement effect, even for the smaller diameters, which results in similar band gaps, similar effective masses, and similar performance metrics. View full abstract»

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  • Layout Variation Effects in Advanced MOSFETs: STI-Induced Embedded SiGe Strain Relaxation and Dual-Stress-Liner Boundary Proximity Effect

    Page(s): 2886 - 2891
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    This paper reports two areas of focus for layout variation effects in advanced strained-Si technology: 1) shallow-trench isolation (STI)-induced embedded SiGe (eSiGe) strain relaxation and 2) impact of dual-stress-liner (DSL) boundary on channel mobility. A complete data analysis, including two different strain measurement techniques of nanobeam diffraction and geometric phase analysis, is presented, along with a quantitative understanding for each effect. It is reported that the eSiGe profile can have a significant impact on the STI proximity effect for p-MOSFETs and that DSL boundary proximity can cause significant channel mobility degradation for both n- and p-MOSFETs. Both effects result in the reduction in channel strain along the [110] direction. View full abstract»

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  • Modeling and Simulation of Charge-Pumping Characteristics for LDD-MOSFET Devices With LOCOS Isolation

    Page(s): 2892 - 2901
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1293 KB) |  | HTML iconHTML  

    We propose a model for the so-called constant-amplitude charge-pumping (CP) characteristics, giving the Elliot Gaussian-like CP current curve (ICP-VL) of lightly doped drain (LDD) MOSFET with local oxidation of silicon (LOCOS). This method is based on modulation of the contributing active-channel area (AG) to the ICP-VL curve, depending on the position of the high and low levels of the gate signal voltage. In addition, it allows to separate and clarify the contribution of all MOSFET regions (such as the effective channel, LDD, LOCOS, and LDD subdiffusion under the LOCOS) to the amount of ICP-VL curves. We have simulated this model and compared with experimental CP data. The model shows a very good correlation with experimental ICP-VL curves, particularly for transistors with short channel gate lengths (LG ≤ 1 μm). However, as the channel gate length increases, the model matches only for rising and falling ICP-VL curve edges, corresponding to the contribution of LDD and LOCOS regions, respectively. Moreover, we have demonstrated that the deviation, which was observed between the CP model and experimental data at the maximum plateau of ICP-VL characteristics, depends on the gate pulse fall time and vanishes for large fall time. This difference has been found to behave like a geometric component, since it depends on gate length and fall time and disappears for both short gate lengths and long fall times. View full abstract»

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  • Dopant-Segregated Schottky Source/Drain FinFET With a NiSi FUSI Gate and Reduced Leakage Current

    Page(s): 2902 - 2906
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (601 KB) |  | HTML iconHTML  

    Enhanced Dopant-segregated Schottky-barrier (DSSB) FinFETs combined with a fully silicided (FUSI) gate were fabricated via single-step Ni-silicidation. Both workfunction control of the gate and a lowered effective SB-height in the source/drain junctions are simultaneously achieved by the dopant-segregated silicidation process. Moreover, the leakage current was significantly reduced with the aid of deep source/drain implantation. Therefore, it can be expected that a DSSB device with a FUSI gate have several advantages as both a logic and nonvolatile memory device. First, for a logic device, it can provide low parasitic resistance and a tunable threshold voltage. Second, for a nonvolatile memory device, the increased workfunction due to the FUSI gate can enhance the erasing characteristics by suppressing the back tunneling of electrons from the gate side as well as the programming characteristics. View full abstract»

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  • Applying Complementary Trap Characterization Technique to Crystalline \gamma -Phase- \hbox {Al}_{2} \hbox {O}_{3} for Improved Understanding of Nonvolatile Memory Operation and Reliability

    Page(s): 2907 - 2916
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    The operation and reliability of nonvolatile memory concepts based on charge storage in nitride layers, such as TANOS (TaN/Al2O3/Si3N4/ SiO2/Si), require detailed information on the energy and spatial distribution of the charge defects in both the nitride and the Al2O3 blocking dielectric. This paper focuses on the characterization of Al2O3. We have successfully applied complementary trap characterization techniques to crystalline γ-phase- Al2O3 in order to obtain a complete picture of the spatial and energetic distribution of the defect density. As a result, two defect types at energy levels 1.8 and 3.5 eV below the conduction band edge are found. View full abstract»

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  • The Equivalent-Thickness Concept for Doped Symmetric DG MOSFETs

    Page(s): 2917 - 2924
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (489 KB) |  | HTML iconHTML  

    In this paper, we propose to derive an analytical model for the doped symmetric double-gate (DG) MOSFET that is valid in all regions of operation. We show that doping the silicon channel can be converted in an equivalent silicon thickness and threshold voltage shift using a formalism developed for the undoped device. Adopting the same physical parameters, we demonstrate that this approach is in agreement with numerical technology computer-aided design simulations. This concept is therefore an interesting basis for a unified model for doped and undoped symmetric DG MOSFETs. View full abstract»

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  • An Analytical I V Model for Surrounding-Gate Transistors That Includes Quantum and Velocity Overshoot Effects

    Page(s): 2925 - 2933
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB) |  | HTML iconHTML  

    A new analytical model is presented for the inversion charge of surrounding-gate transistors (SGTs). Quantum effects are taken into account by means of a modified capacitance model that includes the inversion charge centroid and a correction to the threshold voltage. A drain current model for the SGT that includes velocity saturation, short channel, and velocity overshoot effects is also developed. The model accurately reproduces both simulated and experimental results for different silicon core radii and gate voltages. View full abstract»

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  • Design Optimization of FinFET Domino Logic Considering the Width Quantization Property

    Page(s): 2934 - 2943
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1154 KB) |  | HTML iconHTML  

    Design optimization of FinFET domino logic is particularly challenging due to the unique width quantization property of FinFET devices. Since the keeper device in domino logic is sized based on the leakage current of the pull-down network (PDN) (to meet the noise margin constraint), a reliable statistical framework is required to accurately estimate the domino gate leakage current. Considering the width quantization property, this paper presents such a statistical framework, which provides a reliable design window for keeper sizing to meet the noise margin constraint (for the practical range of threshold voltage variation in sub-32-nm technology nodes). On the other hand, the width quantization property restricts the design optimization (including power/performance characteristics) typically achieved via continuous keeper sizing in planar-CMOS domino logic designs. To cope with this restriction, this paper also introduces a novel methodology for FinFET-based keeper design, which exploits the exclusive property of FinFET devices (capacitive coupling between the front gate and the back gate in a four-terminal FinFET) to simultaneously achieve higher performance and lower power consumption. Using this new methodology, the keeper device is made weaker at the beginning of the evaluation phase to reduce its contention with the PDN, but gradually becomes stronger to provide a higher noise margin. View full abstract»

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  • Suitability Study of Oxide/Gallium Arsenide Interfaces for MOSFET Applications

    Page(s): 2944 - 2956
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (827 KB) |  | HTML iconHTML  

    The suitability of oxide/GaAs interfaces for MOSFET applications has been investigated. Electrical properties of Ga2O3/GaAs interfaces, dielectric stacks utilizing the Ga2O3/GaAs interface, and Al2O3/GaAs interfaces have been studied using a set of independent techniques, including admittance-voltage (ac C-V and G-V at 25°C and 150°C), quasi-static static C-V, photoluminescence intensity (PL-I), and MOSFET I-V measurements. The side-by-side comparison reveals the fundamental differences in their respective data sets. The GdGaO/Ga2O3/GaAs system has been found to exhibit a U-shaped Dit distribution with a midgap Dit plateau of 2 - 3 × 1011 cm-2 · eV-1, which has allowed manufacturing GaAs MOSFETs with dc performance close to ideal model predictions. Some other ternary oxides such as GdScO3 and LaAlO3 can also be deposited on a Ga2O3 template without disrupting the Ga2O3/GaAs interface. Beyond GaAs bulk, the use of a surface heterostructure has been investigated, which shifts, in energy space, the mobile charge distribution in the channel layer away from a branch of rising Dit in the vicinity of Ec at the Ga2O3/GaAs interface. In contrast, Al2O3/GaAs(100) interfaces show a typical GaAs native oxide behavior with a <;5-shaped Dit distribution centered around the midgap and a pinned Fermi level. Although this study has been conducted with the objective of developing GaAs MOSFETs for RF power applications, it is recommended to apply an identical set of independent analytical techniques to the characterization of dielectric/semiconductor interfaces which are of interest for high-mobility CMOS channels such as InxGa1-xAs. View full abstract»

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  • Correlation Between Measured Minority-Carrier Lifetime and \hbox {Cu}( \hbox {In}, \hbox {Ga})\hbox {Se}_{2} Device Performance

    Page(s): 2957 - 2963
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB) |  | HTML iconHTML  

    The relationship between lifetime measured by time-resolved photoluminescence on bare Cu(In, Ga)Se2 films and subsequent device performance is examined. Devices and films from both the laboratory and a 40-MW manufacturing line are examined. A correlation between the device voltage and lifetime is demonstrated. The effects of the measured band gap and carrier density are discussed. A method to account for the effects of varying band-gap and carrier density profiles, without requiring computer modeling, is presented. Results are compared with fundamental calculations. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology