IEEE Transactions on Computers

Issue 12 • Dec 1992

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Displaying Results 1 - 17 of 17
  • Learning probabilistic RAM nets using VLSI structures

    Publication Year: 1992, Page(s):1552 - 1561
    Cited by:  Papers (34)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (932 KB)

    Hardware-realizable learning probabilistic RAMs (pRAMs) which implement local reinforcement rules utilizing synaptic rather than threshold noise in the stochastic search procedure are described. The design allows for both global and local rewards and penalties (in this latter case implementing a modified version of backpropagation). The architecture allows for serial updating of the weights of a p... View full abstract»

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  • Efficient instruction sequencing with inline target insertion

    Publication Year: 1992, Page(s):1537 - 1551
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1308 KB)

    Inline target insertion, a specific compiler and pipeline implementation method for delayed branches with squashing, is defined. The method is shown to offer two important features not discovered in previous studies. First, branches inserted into branch slots are correctly executed. Second, the execution returns correctly from interrupts or exceptions with only one program counter. These two featu... View full abstract»

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  • An algorithm for the efficient utilization of bandwidth in the slotted ring

    Publication Year: 1992, Page(s):1620 - 1627
    Cited by:  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    The slotted ring local area network is very efficient under light load, but suffers from severe performance degradations as the load increases, especially if message sizes are highly variable. An algorithm is presented, in the form of a medium access protocol, to allow for the efficient utilization of the bandwidth of the slotted ring. The protocol is based on the release of slots by destination s... View full abstract»

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  • An approximation algorithm for scheduling tasks on varying partition sizes in partitionable multiprocessor systems

    Publication Year: 1992, Page(s):1572 - 1579
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (820 KB)

    A partitionable multiprocessor system can form multiple partitions, each consisting of a controller and a varying number of processors. Given such a system and a set of tasks, each of which can be executed on partitions of varying sizes, the authors study the problem of choosing the partition sizes and a minimum completion time schedule for the execution of these tasks. They assume that the number... View full abstract»

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  • Robust and nonrobust path delay fault simulation by parallel processing of patterns

    Publication Year: 1992, Page(s):1527 - 1536
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (912 KB)

    An accelerated fault simulation approach for path delay faults is presented. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and nonrobust decision of path delay faults, and its capability of efficiently maintaining large numbers of path... View full abstract»

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  • Concurrent error detection and correction in real-time systolic sorting arrays

    Publication Year: 1992, Page(s):1615 - 1620
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    A novel approach to online error detection and correction for high-throughput VLSI sorting arrays is presented. The error model is defined at the sorting element level and both functional errors and data errors are considered. Functional errors are detected and corrected by exploiting inherent properties as well as newly discovered special properties of the sorting array. Coding techniques are use... View full abstract»

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  • On-the-fly rounding [computing arithmetic]

    Publication Year: 1992, Page(s):1497 - 1503
    Cited by:  Papers (31)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    In implementations of operations based on digit-recurrence algorithms such as division, left-to-right multiplication and square root, the result is obtained in digit-serial form, from most significant digit to least significant. To reduce the complexity of the result-digit selection and allow the use of redundant addition, the result-digit has values from a signed-digit set. As a consequence, the ... View full abstract»

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  • Design of a radix 4 division unit with simple selection table

    Publication Year: 1992, Page(s):1606 - 1611
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    A radix 4 division architecture is presented which partially overlaps the updating of the remainder with the digit selection procedure. It is obtained by separating the radix 4 digit selection process into two concurrent substeps. The proposed unit requires a simple selection table and involves a small extra expense for the additional hardware compared to the usual radix 4 division units. Four pos... View full abstract»

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  • Parallel signature analyzers using hybrid design of their linear feedbacks

    Publication Year: 1992, Page(s):1562 - 1571
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB)

    A bottom-top exclusive OR (BTE) type multiple input linear feedback shift register (MISR) and a top-bottom exclusive OR (TBE) type MISR which use only (t+1)/2 XOR gates in their linear feedback are presented. An algebraic analysis of the operation and certain analytical results regarding the detection capability of a BTE MISR are included. Infirmities of certain BTE type MISRs and TBE typ... View full abstract»

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  • A Benes-like theorem for the shuffle-exchange graph

    Publication Year: 1992, Page(s):1627 - 1630
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    One of the first theorems on permutation routing, proved by V.E. Benes (1965), shows that give a set of source-destination pairs in an N-node butterfly network with at most a constant number of sources or destinations in each column of the butterfly, there exists a set of paths of lengths O(log N) connecting each pair such that the total congestion is constant. An analog... View full abstract»

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  • Bounding signal probabilities for testability measurement using conditional syndromes

    Publication Year: 1992, Page(s):1580 - 1588
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    An algorithm for bounding the random pattern testability of individual faults in a circuit is proposed. Auxiliary gates for bounding the testability are constructed, converting the problem into one of determining the signal probability at the output of the auxiliary gate. The results presented are in terms of lower bounds of the testabilities of faults. The bounds generated by the algorithm can be... View full abstract»

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  • FOCUS: an experimental environment for fault sensitivity analysis

    Publication Year: 1992, Page(s):1515 - 1526
    Cited by:  Papers (45)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1068 KB)

    FOCUS, a simulation environment for conducting fault-sensitivity analysis of chip-level designs, is described. The environment can be used to evaluate alternative design tactics at an early design stage. A range of user specified faults is automatically injected at runtime, and their propagation to the chip I/O pins is measured through the gate and higher levels. A number of techniques for fault-s... View full abstract»

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  • High-speed addition in CMOS

    Publication Year: 1992, Page(s):1612 - 1615
    Cited by:  Papers (30)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (724 KB)

    A fully static complementary metal-oxide semiconductor (CMOS) implementation of a Ling-type 32-bit adder is described. The implementation saves up to one gate delay and always reduces the number of serial transistors in the worst-case critical path over the conventional carry look-ahead (CLA) approach with a negligible increaser in hardware View full abstract»

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  • On the relationship between two systolic array design methodologies

    Publication Year: 1992, Page(s):1589 - 1593
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    The parameter method and data dependency method have been proposed as systematic design methodologies for systolic arrays. The authors describe the relationship between the two methodologies and show that the parameter method applies to a subclass of the algorithms that can be processed by the dependency method. The optimization procedure of the parameter method can be applied, in a restricted sen... View full abstract»

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  • Recovering from multiple process failures in the time warp mechanism

    Publication Year: 1992, Page(s):1504 - 1514
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1100 KB)

    A recovery protocol for distributed systems using the time warp control mechanism is described. The proposed protocol is fault tolerant to multiple process failures. Time warp is an optimistic execution technique in which synchronization is achieved using rollback. The recovery protocol exploits the redundancy already available to implement process rollback in the time warp mechanism. Thus, the pr... View full abstract»

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  • A fast Faddeev array

    Publication Year: 1992, Page(s):1594 - 1600
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    A systolic array for the fast computation of the Faddeev algorithm is presented. Inversion of an n×n matrix on a systolic array is known to tend to 5 n inner product steps under the assumption that no data are duplicated. The proposed Faddeev array achieves matrix inversion in just 4 n steps with O (n2) basic cells using carefu... View full abstract»

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  • Byte unidirectional error correcting and detecting codes

    Publication Year: 1992, Page(s):1601 - 1606
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    Efficient byte unidirectional error correcting codes that are better than byte symmetric error correcting codes are presented. The encoding and decoding algorithms are discussed. A lower bound on the number of check bits for byte unidirectional error correcting codes is derived. It is then shown that these codes are close to optimal. Capability of these codes for asymmetric error correction is als... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org