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# IEEE Transactions on Circuits and Systems I: Regular Papers

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Displaying Results 1 - 25 of 28
• ### Table of contents

Publication Year: 2010, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2010, Page(s): C2
| PDF (135 KB)
• ### A 3-GHz Serial ATA Spread-Spectrum Clock Generator Employing a Chaotic PAM Modulation

Publication Year: 2010, Page(s):2577 - 2587
Cited by:  Papers (24)
| | PDF (1570 KB) | HTML

In this paper, we propose a prototype of a spread-spectrum clock generator which is the first known specifically meant generator for 3-GHz Serial Advanced Technology Attachment II (SATA-II) applications. A further innovative aspect of our prototype is that it takes advantage of a chaotic pulse-amplitude modulation as driving signal, instead of a triangular signal as in all spread-spectrum generato... View full abstract»

• ### An Area-Efficient Fully R-DAC-Based TFT-LCD Column Driver

Publication Year: 2010, Page(s):2588 - 2601
Cited by:  Papers (14)
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This paper proposes an area-efficient fully resistor-string digital-to-analog-converter (R-DAC)-based thin-film transistor liquid crystal display (TFT-LCD) column driver in which DACs supply only negative-polarity voltages, while polarity inverters generate positive-polarity voltages from negative-polarity voltages. An offset cancellation technique is employed in negative-polarity buffers and pola... View full abstract»

• ### On Two-Phase Switched-Capacitor Multipliers With Minimum Circuit Area

Publication Year: 2010, Page(s):2602 - 2608
Cited by:  Papers (24)
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This paper compares the performance among two-phase switched-capacitor multipliers to identify the optimum topology with the smallest circuit area. The optimum number of stages is calculated for every multiplier to minimize the circuit area under the condition that a certain current is outputted with a given output voltage. Then, the circuit areas of the serial-parallel, linear (LIN), Fibonacci, a... View full abstract»

• ### Wideband Varactorless $LC$ VCO Using a Tunable Negative-Inductance Cell

Publication Year: 2010, Page(s):2609 - 2617
Cited by:  Papers (15)  |  Patents (3)
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A wideband LC voltage-controlled oscillator (VCO) design with a new varactorless frequency-tuning technique is presented. The wideband continuous frequency tuning is achieved using a tunable negative-inductance cell. Fabricated in a 0.35-μm SiGe BiCMOS process, the varactorless VCO achieves a continuous tuning range of 24.5%. An overall tuning range of 31% from 3.8 to 5.2 GHz is achieved wh... View full abstract»

• ### Unified Frequency-Domain Analysis of Switched-Series-$RC$ Passive Mixers and Samplers

Publication Year: 2010, Page(s):2618 - 2631
Cited by:  Papers (38)
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A wide variety of voltage mixers and samplers are implemented with similar circuits employing switches, resistors, and capacitors. Restrictions on duty cycle, bandwidth, or output frequency are commonly used to obtain an analytical expression for the response of these circuits. This paper derives unified expressions without these restrictions. To this end, the circuits are decomposed into a polyph... View full abstract»

• ### A Five-Decade Dynamic-Range Ambient-Light-Independent Calibrated Signed-Spatial-Contrast AER Retina With 0.1-ms Latency and Optional Time-to-First-Spike Mode

Publication Year: 2010, Page(s):2632 - 2643
Cited by:  Papers (20)
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Address Event Representation (AER) is an emergent technology for assembling modular multiblock bio-inspired sensory and processing systems. Visual sensors (retinae) are among the first AER modules to be reported since the introduction of the technology. Spatial-contrast AER retinae are of special interest since they provide highly compressed data flow without reducing the relevant information requ... View full abstract»

• ### Nonlinear R-2R Transistor-Only DAC

Publication Year: 2010, Page(s):2644 - 2653
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A nonlinear current-division technique is proposed with the design parameters on the aspect ratio of transistors only. The design approach uses the linear voltage-to-current relation for MOS transistors in the triode region. The nonlinear characteristics of the output current can be obtained by adding additional transistors on the conventional R-2R transistor-only ladder. This work can be employed... View full abstract»

• ### UWB CMOS Monocycle Pulse Generator

Publication Year: 2010, Page(s):2654 - 2664
Cited by:  Papers (28)
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A low-complexity fully integrated ultrawideband (UWB) monocycle pulse generator realized in 90-nm CMOS technology by ST-Microelectronics is presented. The circuit provides a monocycle pulse when activated by a negative edge of an external trigger signal provided by a microcontroller by exploiting the operating principle of nonlinear waveform shapers. This pulse generator represents a building bloc... View full abstract»

• ### A 20-GS/s 5-b SiGe ADC for 40-Gb/s Coherent Optical Links

Publication Year: 2010, Page(s):2665 - 2674
Cited by:  Papers (11)
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A 10-GBd 40-Gb/s coherent optical transport is a promising technology for higher data rate communications by virtue of improved sensitivity and high spectrum efficiency. One of the major challenges in designing a 40-Gb/s coherent quadrature-phase-shift-keying receiver is to achieve high-speed data conversion at around 20-GHz sampling rate with at least 5-bit resolution. With the detailed design fr... View full abstract»

• ### An Energy-Aware CMOS Receiver Front End for Low-Power 2.4-GHz Applications

Publication Year: 2010, Page(s):2675 - 2684
Cited by:  Papers (21)
| | PDF (918 KB) | HTML

A receiver front end designed in 0.18- μm CMOS consisting of a low-noise amplifier and IQ mixers is presented. The front end's power consumption is controllable from 5.0 down to 1.4 mA. It is proposed to push the receiver requirements to the front end in order to efficiently control the overall power consumption based on the real-time required noise performance. We show that, under good cha... View full abstract»

• ### A High-Gain Power-Matching Technique for Efficient Radio-Frequency Power Harvest of Passive Wireless Microsystems

Publication Year: 2010, Page(s):2685 - 2695
Cited by:  Papers (13)
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This paper proposes a transformer power-matching and gain-boosting technique to improve the efficiency of power harvesting of passive wireless microsystems. The proposed method utilizes a step-up transformer inserted between the antenna and voltage multiplier of passive wireless microsystems to perform both impedance transformation for power matching and voltage amplification prior to rectificatio... View full abstract»

• ### Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems

Publication Year: 2010, Page(s):2696 - 2707
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This paper proposes a novel solution to make asynchronous handshake interfaces tolerant to crosstalk-glitch propagation (GP). This study leverages our recently proposed crosstalk-glitch modeling technique for asynchronous systems, which models the crosstalk GP in asynchronous interfaces. In this paper, a novel set of solutions to quench the GP is proposed. This set of solutions is called crosstalk... View full abstract»

• ### Quaternion Multiplier Inspired by the Lifting Implementation of Plane Rotations

Publication Year: 2010, Page(s):2708 - 2717
Cited by:  Papers (10)
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A lifting-based structure for quaternion multipliers with unit-magnitude constant coefficients is proposed, whose development was inspired by the well-known implementation of a plane rotation (complex multiplication with a unit-magnitude coefficient) using three shears each of which corresponds to one real multiplication and addition. Our solution is mainly aimed at implementing quaternion transfo... View full abstract»

• ### Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory

Publication Year: 2010, Page(s):2718 - 2728
Cited by:  Papers (77)  |  Patents (1)
| | PDF (666 KB) | HTML

With the appealing storage-density advantage, multilevel-per-cell (MLC) NAND Flash memory that stores more than 1 bit in each memory cell now largely dominates the global Flash memory market. However, due to the inherent smaller noise margin, the MLC NAND Flash memory is more subject to various device/circuit variability and noise, particularly as the industry is pushing the limit of technology sc... View full abstract»

• ### A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform

Publication Year: 2010, Page(s):2729 - 2740
Cited by:  Papers (7)
| | PDF (619 KB) | HTML

In this paper, a scheme for the design of a high-speed pipeline VLSI architecture for the computation of the 1-D discrete wavelet transform (DWT) is proposed. The main focus of the scheme is on reducing the number and period of clock cycles for the DWT computation with little or no overhead on the hardware resources by maximizing the inter- and intrastage parallelisms of the pipeline. The intersta... View full abstract»

• ### Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs

Publication Year: 2010, Page(s):2741 - 2752
Cited by:  Papers (2)
| | PDF (993 KB) | HTML

Chip heating and nonuniform distribution of hot and cool zones on the die negatively affect reliability and robustness to failures of nanometer integrated circuits. In fact, signal propagation on interconnects slows down as temperature rises; for long wires crossing regions at different temperatures, such as the clock network, thermally induced delay and skew get altered and may result in timing f... View full abstract»

• ### Small-Area and Low-Energy $K$-Best MIMO Detector Using Relaxed Tree Expansion and Early Forwarding

Publication Year: 2010, Page(s):2753 - 2761
Cited by:  Papers (18)
| | PDF (1256 KB) | HTML

This paper proposes a new K-best detection method that is efficient in area and energy consumption. To reduce the complexity required in tree expansion and sorting, some children of a candidate are not expanded if they are estimated as inferior ones, and they are not considered in the sorting. In addition, we propose an efficient pipeline scheduling called early forwarding to reduce the overall pr... View full abstract»

• ### Modulation Flexibility in PLC: A Unified MCM Transceiver Design and Implementation

Publication Year: 2010, Page(s):2762 - 2775
Cited by:  Papers (3)  |  Patents (2)
| | PDF (725 KB) | HTML

Multicarrier modulations (MCMs) have been considered as a good means to combat the frequency-selective fading. In practice, the MCM idea has already been integrated in most of the modern communication applications, including power line communications (PLCs). However, even in the MCM conception, there still exist several proposals of different schemes that remain competing with each other. In this ... View full abstract»

• ### Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures

Publication Year: 2010, Page(s):2776 - 2789
Cited by:  Papers (21)
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This paper proposes a general framework for the design and simulation of network-on-chip-based turbo decoder architectures. Several parameters in the design space are investigated, namely, network topology, parallelism degree, the rate at which messages are sent by processing nodes over the network, and routing strategy. The main results of this analysis are as follows: 1) the most suited topologi... View full abstract»

• ### A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes

Publication Year: 2010, Page(s):2790 - 2803
Cited by:  Papers (20)
| | PDF (1306 KB) | HTML

For an efficient multimode low-density parity-check (LDPC) decoder, most hardware resources, such as permutators, should be shared among different modes. Although an LDPC code constructed based on a Reed-Solomon (RS) code with two information symbols is not quasi-cyclic, in this paper, we reveal that the structural properties inherent in its parity-check matrix can be adopted in the design of conf... View full abstract»

• ### An Integrated Speed- and Accuracy-Enhanced CMOS Current Sensor With Dynamically Biased Shunt Feedback for Current-Mode Buck Regulators

Publication Year: 2010, Page(s):2804 - 2814
Cited by:  Papers (37)  |  Patents (2)
| | PDF (2691 KB) | HTML

This paper presents a new compact on-chip current-sensing circuit to enable current-mode buck regulators operating at a high switching frequency for reducing the inductor profile. A dynamically biased shunt feedback technique is developed in the proposed current sensor to push nondominant poles to higher frequencies, thereby improving the speed and stability of the current sensor under a wide rang... View full abstract»

• ### Push–Pull Forward Three-Level Converter With Reduced Rectifier Voltage Stress

Publication Year: 2010, Page(s):2815 - 2821
Cited by:  Papers (7)
| | PDF (748 KB) | HTML

This paper proposes a push-pull forward three-level (TL) converter, which is suitable for low and wide-range input-voltage applications, such as fuel cell and solar cell. Half of the switches sustain half of the input voltage, and the others sustain one and one-half input voltage. The input ripple current and output filter inductor ripple current can be reduced with TL waveform of the secondary re... View full abstract»

• ### IEEE Transactions on Circuits and Systems—I: Regular Papers Information for authors

Publication Year: 2010, Page(s): 2822
| PDF (119 KB)

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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## Meet Our Editors

Editor-in-Chief

Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK