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IEEE Transactions on Computers

Issue 11 • Nov. 2010

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Displaying Results 1 - 16 of 16
  • [Front cover]

    Publication Year: 2010, Page(s): c1
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    Freely Available from IEEE
  • [Inside front cover]

    Publication Year: 2010, Page(s): c2
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  • Speculatively Redundant Continued Logarithm Representation

    Publication Year: 2010, Page(s):1441 - 1454
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2335 KB) | HTML iconHTML Multimedia Media

    Continued logarithms, as originally introduced by Gosper, represent a means for exact rational arithmetic, but their application to exact real arithmetic is limited by the uniqueness of their representation. This is quite unfortunate, as this representation seems promising for efficient hardware implementation. We propose an idea of making the representation redundant using speculative recognition... View full abstract»

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  • High-Performance Robust Latches

    Publication Year: 2010, Page(s):1455 - 1465
    Cited by:  Papers (32)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2197 KB) | HTML iconHTML

    First, a new high-performance robust latch (referred to as HiPeR latch) is presented that is insensitive to transient faults affecting its internal and output nodes by design, independently of the size of its transistors. Then, a modified version of the HiPeR latch (referred as HiPeR-CG) is proposed that is suitable to be used together with clock gating. Both proposed latches are faster than the l... View full abstract»

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  • Transparent Fault Tolerance of Device Drivers for Virtual Machines

    Publication Year: 2010, Page(s):1466 - 1479
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2342 KB) | HTML iconHTML

    In a consolidated server system using virtualization, physical device accesses from guest virtual machines (VMs) need to be coordinated. In this environment, a separate driver VM is usually assigned to this task to enhance reliability and to reuse existing device drivers. This driver VM needs to be highly reliable, since it handles all the I/O requests. This paper describes a mechanism to detect a... View full abstract»

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  • Conditional Partial Order Graphs: Model, Synthesis, and Application

    Publication Year: 2010, Page(s):1480 - 1493
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3952 KB) | HTML iconHTML

    The paper introduces a new formal model for specification and synthesis of control paths in the context of asynchronous system design. The model, called Conditional Partial Order Graph (CPOG), captures concurrency and choice in a system's behavior in a compact and efficient way. It has advantages over widely used interpreted Petri Nets and Finite State Machines for a class of systems which have ma... View full abstract»

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  • Cache-Based Memory Copy Hardware Accelerator for Multicore Systems

    Publication Year: 2010, Page(s):1494 - 1507
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2228 KB) | HTML iconHTML

    In this paper, we present a new architecture of the cache-based memory copy hardware accelerator in a multicore system supporting message passing. The accelerator is able to accelerate memory data movements, in particular memory copies. We perform an analytical analysis based on open-queuing theory to study the utilization of our accelerator in a multicore system. In order to correctly model the s... View full abstract»

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  • Improving Networked File System Performance Using a Locality-Aware Cooperative Cache Protocol

    Publication Year: 2010, Page(s):1508 - 1519
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2140 KB) | HTML iconHTML

    In a distributed environment, the utilization of file buffer caches in different clients may greatly vary. Cooperative caching has been proposed to increase cache utilization by coordinating the shared usage of distributed caches. It allows clients that would more greatly benefit from larger caches to forward data objects to peer clients with relatively underutilized caches. To support such coordi... View full abstract»

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  • Accurate Determination of Loop Iterations for Worst-Case Execution Time Analysis

    Publication Year: 2010, Page(s):1520 - 1532
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1704 KB) | HTML iconHTML

    Determination of accurate estimates for the Worst-Case Execution Time of a program is essential for guaranteeing the correct temporal behavior of any Real-Time System. Of particular importance is tightly bounding the number of iterations of loops in the program or excessive undue pessimism can result. This paper presents a novel approach to determining the number of iterations of a loop for such a... View full abstract»

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  • A Novel Cryptoprocessor Architecture for the McEliece Public-Key Cryptosystem

    Publication Year: 2010, Page(s):1533 - 1546
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2820 KB) | HTML iconHTML

    The McEliece public-key cryptosystem relies on the NP-hard decoding problem, and therefore, is regarded as a solution for postquantum cryptography. Though early known, this cryptosystem was not employed so far because of efficiency questions regarding performance and communication overhead. This paper presents a novel processor architecture as a high-performance platform to execute key generation,... View full abstract»

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  • Reconfigurable Hardware Implementations of Tweakable Enciphering Schemes

    Publication Year: 2010, Page(s):1547 - 1561
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4134 KB) | HTML iconHTML

    Tweakable enciphering schemes are length-preserving block cipher modes of operation that provide a strong pseudorandom permutation. It has been suggested that these schemes can be used as the main building blocks for achieving in-place disk encryption. In the past few years, there has been an intense research activity toward constructing secure and efficient tweakable enciphering schemes. But actu... View full abstract»

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  • Heterogenous Quorum-Based Wake-Up Scheduling in Wireless Sensor Networks

    Publication Year: 2010, Page(s):1562 - 1575
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1810 KB) | HTML iconHTML

    We present heterogenous quorum-based asynchronous wake-up scheduling schemes for wireless sensor networks. The schemes can ensure that two nodes that adopt different quorum systems as their wake-up schedules can hear each other at least once in bounded time intervals. We propose two such schemes: cyclic quorum system pair (cqs-pair) and grid quorum system pair (gqs-pair). The cqs-pair which contai... View full abstract»

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  • A Counter Architecture for Online DVFS Profitability Estimation

    Publication Year: 2010, Page(s):1576 - 1583
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1767 KB) | HTML iconHTML

    Dynamic voltage and frequency scaling (DVFS) is a well known and effective technique for reducing power consumption in modern microprocessors. An important concern though is to estimate its profitability in terms of performance and energy. Current DVFS profitability estimation approaches, however, lack accuracy or incur runtime performance and/or energy overhead. This paper proposes a counter arch... View full abstract»

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  • IEEE Computer Society CSDP Certification [advertisement]

    Publication Year: 2010, Page(s): 1584
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    Freely Available from IEEE
  • TC Information for authors

    Publication Year: 2010, Page(s): c3
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    Freely Available from IEEE
  • [Back cover]

    Publication Year: 2010, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org