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Solid-State Circuits, IEEE Journal of

Issue 10 • Date Oct. 2010

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Displaying Results 1 - 25 of 33
  • Table of contents

    Publication Year: 2010 , Page(s): C1 - C4
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  • IEEE Journal of Solid-State Circuits publication information

    Publication Year: 2010 , Page(s): C2
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  • Table of contents

    Publication Year: 2010 , Page(s): 1957 - 1958
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  • Introduction to the 31st Annual IEEE Compound Semiconductor Integrated Circuit Symposium

    Publication Year: 2010 , Page(s): 1959 - 1960
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  • A 120–145 GHz Heterodyne Receiver Chipset Utilizing the 140 GHz Atmospheric Window for Passive Millimeter-Wave Imaging Applications

    Publication Year: 2010 , Page(s): 1961 - 1967
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (740 KB) |  | HTML iconHTML  

    For passive mm-wave imaging applications, broadband mm-wave receivers functioning within atmospheric windows are highly desired. Within this paper, a heterodyne receiver chipset utilizing the 140 GHz atmospheric window is presented. The heterodyne chipset is based on two different millimeter-wave monolithic integrated circuits (MIMICs). One is the receiver MIMIC including a low-noise amplifier, a down-conversion mixer, a frequency multiplier and a local oscillator buffer amplifier together with a local oscillator distribution network. The other is a voltage-controlled oscillator (VCO) working in the 35 GHz frequency range to generate the local oscillator signal for the receiver (down-converter) chip. The process technology chosen to realize the chipset is a 100 nm gatelength metamorphic InAlAs/InGaAs high electron mobility transistor (HEMT) technology on 50 μm thick and 4 inch diameter GaAs substrates. The chips are utilizing a grounded coplanar waveguide (GCPW) technology. For an operation frequency band from 120 to 145 GHz, the receiver demonstrates a flat conversion gain between -1 and +2 dB with a power consumption of 120 mW. The VCO is tuneable from 31 to 37 GHz with associated output power levels from -2 to +1 dBm. Detailed descriptions of the individual building blocks are given and measured results are presented for the building blocks as well as for the receiver. View full abstract»

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  • An 18-Gb/s, Direct QPSK Modulation SiGe BiCMOS Transceiver for Last Mile Links in the 70–80 GHz Band

    Publication Year: 2010 , Page(s): 1968 - 1980
    Cited by:  Papers (30)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3341 KB) |  | HTML iconHTML  

    This paper describes a single-chip, 70-80 GHz wireless transceiver utilizing a direct mm-wave QPSK modulator. The transceiver was fabricated in a 130 nm SiGe BiCMOS technology and can operate at data rates in excess of 18 Gb/s. The peak gain of the zero-IF receiver is 50 dB, the double sideband noise figure remains below 7 dB, while the 3-dB receive-chain bandwidth extends from DC to over 6 GHz. The differential transmitter achieves a maximum output power of +9 dBm. The total power consumption of the 1.9 mm × 1.1 mm transceiver is 1.2 W from 1.5, 2.5 and 3.3 V power supplies, including the 4 × 20-Gb/s PRBS generator. View full abstract»

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  • A Passive W-Band Imaging Receiver in 65-nm Bulk CMOS

    Publication Year: 2010 , Page(s): 1981 - 1991
    Cited by:  Papers (32)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1683 KB) |  | HTML iconHTML  

    A passive imaging receiver operating in the W-band around 90 GHz has been realized in a digital 65-nm CMOS process. The circuit, occupying only 0.41 mm2, integrates an SPDT switch with 4.2 dB loss and 25 dB isolation, a five-stage telescopic cascode LNA with 27 dB gain at 90 GHz, and a W-band square-law detector, all consuming less than 33 mA from 1.2 V. A version of the receiver without the input SPDT switch has a peak responsivity of over 200 kV/W and a minimum NEP of less than 0.1 pW/ Hz. The full Dicke radiometer, which includes the input switch, achieves a responsivity of 90 kV/W and an NEP of 0.2 pW/ Hz. This work represents the first W-band passive imaging receiver to be implemented in standard CMOS with this level of integration. View full abstract»

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  • A 0.25 \mu m InP DHBT 200 GHz+ Static Frequency Divider

    Publication Year: 2010 , Page(s): 1992 - 2002
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3599 KB) |  | HTML iconHTML  

    Static frequency dividers are widely used technology performance benchmark circuits. Using a 0.25 μm 530 GHz fT /600 GHz+ fmax InP DHBT process, a static frequency divider circuit has been designed, fabricated, and measured to operate up to 200.6 GHz. The divide-by-two core flip-flop dissipates 228 mW. Techniques used for the divider design optimization and for selecting variants to maximize performance across process changes are also discussed. View full abstract»

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  • A Low-Loss 50–70 GHz SPDT Switch in 90 nm CMOS

    Publication Year: 2010 , Page(s): 2003 - 2007
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (805 KB) |  | HTML iconHTML  

    This paper presents an ultra-low-loss 50-70 GHz single-pole double-throw (SPDT) switch built using a standard 90 nm CMOS process. The switch is based on λ/4 transmission lines with shunt inductors at the output matching network. The SPDT switch results in a measured insertion loss of 1.5-1.6 dB at 53-60 GHz and <; 2.0 dB at 50-70 GHz. The measured isolation is >25 dB, and the output port-to-port isolation is > 27 dB at 50-70 GHz. The measured P1dB is 13.5 dBm with a corresponding IIP3 of 22.5 dBm at 60 GHz. The return loss is better than -8 dB at 50-70 GHz. The active chip area is 0.5 × 0.55 mm2 and can be reduced in future designs by folding the on λ/4 transmission lines. To our knowledge, this paper presents the lowest insertion loss 60 GHz SPDT in any CMOS technology. View full abstract»

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  • MMIC LNAs for Radioastronomy Applications Using Advanced Industrial 70 nm Metamorphic Technology

    Publication Year: 2010 , Page(s): 2008 - 2015
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1787 KB) |  | HTML iconHTML  

    Radioastronomy applications, as well as others, require ultra-low-noise front ends for high-sensitivity receivers. In this way, the image produced from a radio-telescope using such advanced components has a higher resolution and therefore allows scientists to obtain a clearer representation of the environment. The low-noise amplifier is the key component of a high sensitivity receiver (demonstrating a very low noise figure, even in the millimeter-wave frequency region). Such electrical performance is obtained from the combined use of an advanced technology (fT and fmax > 250 GHz, LG <; 0, 1 μm) and appropriate design methodologies that take into account electrical specifications and system constraints in the context of the targeted application. In this contribution, we will present both the performance of the employed technology (OMMIC 70 nm GaAs mHEMT) and the related low-noise design methodologies that have led to the realization of four different LNAs operating from 5 GHz up to 100 GHz and beyond. View full abstract»

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  • A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

    Publication Year: 2010 , Page(s): 2016 - 2029
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2995 KB) |  | HTML iconHTML  

    A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package. View full abstract»

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  • High Efficiency WCDMA Power Amplifier With Pulsed Load Modulation (PLM)

    Publication Year: 2010 , Page(s): 2030 - 2037
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (996 KB) |  | HTML iconHTML  

    Complex non-constant-envelope modulations are often used in wireless communications. A power amplifier (PA) is developed based on the concept of pulsed load modulation (PLM) that can enhance the power efficiency of the PA when the output power is back off from the peak due to modulations. The PLM technique utilizes the time-varying behavior of switched resonators to form an optimal, power dependent load impedance. The switched resonator consists of a balanced pair of switching mode PAs that drive a high-Q bandpass filter. In addition to its efficiency enhancement through PLM, the PA is able to preserve the linearity of complex modulations through the architecture of envelope delta-sigma modulation (EDSM). In this paper, a 1.87 GHz PLM power amplifier is fabricated with a pair of 0.35 μm GaAs pHEMT devices. The duty cycle tests show its significant improvement on power efficiency at different back-off levels over traditional Class-B amplifiers. The PA module is also tested with a single-channel WCDMA signal with peak to average ratio (PAR) of 10.8 dB. It has achieved 39 dBc adjacent channel leakage ratio (ACLR) at 5 MHz offsets without needing additional linearization techniques. The power added efficiency in this case is 43% including the loss of the output filter and 52.6% if the loss of the filter is de-embedded. View full abstract»

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  • A Highly Linear Two-Stage Amplifier Integrated Circuit Using InGaP/GaAs HBT

    Publication Year: 2010 , Page(s): 2038 - 2043
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2124 KB) |  | HTML iconHTML  

    This paper presents a linearized two-stage amplifier integrated circuit (IC), having an output power level of about 1 Watt, used for general purpose applications. A predistortion method, based on alignment of the nonlinear characteristics between the first- and the second-stage amplifiers, has been proposed and analyzed in order to enhance the linearization aspects. The resistors in the active bias circuits of both the stages are optimized to achieve the best cancellation conditions for the third-order intermodulation components. The two-stage amplifier IC, which is based on an InGaP/GaAs hetero-junction bipolar transistor (HBT) technology, has been designed and implemented for the 900 MHz band. An output 1 dB compression point (P1dB) of 29.6 dBm, a maximum third-order output intercept point (OIP3) of as high as 48.7 dBm at a two-tone average output power of 21 dBm have been obtained while having a quiescent current of 375 mA and a single bias supply of 5.5 V. The implemented amplifier is able to maintain its IMD3 performance below -60 dBc up to an output power of 21 dBm. View full abstract»

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  • A 140 dB-CMRR Current-Feedback Instrumentation Amplifier Employing Ping-Pong Auto-Zeroing and Chopping

    Publication Year: 2010 , Page(s): 2044 - 2056
    Cited by:  Papers (14)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1071 KB) |  | HTML iconHTML  

    This paper presents a precision general-purpose current-feedback instrumentation amplifier (CFIA) that employs a combination of ping-pong auto-zeroing and chopping to cancel its offset and 1/f noise. A comparison of offset-cancellation techniques shows that neither chopping nor auto-zeroing is an ideal solution for general-purpose CFIAs, since chopping results in output ripple, and auto-zeroing is associated with increased low-frequency noise. The presented CFIA mitigates these unintended side effects through a combination of these techniques. A ping-pong auto-zeroed input stage with slow-settling offset-nulling loops is applied to limit the bandwidth of the increased noise to less than half of the auto-zeroing frequency. This noise is then modulated away from DC by chopping the input stage at half the auto-zeroing frequency, reducing the low-frequency noise to the 27 nV/ white-noise level, without introducing extra output ripple. The auto-zeroing is augmented with settling phases to further reduce output transients. The CFIA was realized in a 0.5 μm analog CMOS process and achieves a typical offset of 2.8 μV and a CMRR of 140 dB in a common-mode voltage range that includes the negative supply. View full abstract»

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  • An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing

    Publication Year: 2010 , Page(s): 2057 - 2065
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1733 KB) |  | HTML iconHTML  

    A small-size inductive-coupling dc voltage transceiver for highly-parallel wafer-level testing is experimentally demonstrated in 90-nm CMOS technology, which can reduce the total cost of a low-price IC by 18%. In order to carry out dc tests, the proposed transceiver outputs dc voltage to the die-under-test (DUT) without any area-consuming digital circuits. In addition, digital calibration with digital feedback channel which calibrates the output dc voltage enables the removal of calibration circuits on the DUT. All of the circuits for dc tests are implemented into the area of an inductor (100 μm ×100 μm). The proposed dc voltage transmission is successfully demonstrated with 6-bit resolution. View full abstract»

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  • A Delta-Sigma Pulse-Width Digitization Technique for Super-Regenerative Receivers

    Publication Year: 2010 , Page(s): 2066 - 2079
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2797 KB) |  | HTML iconHTML  

    This paper presents a delta-sigma pulse-width digitizer (ΔΣ-PWD) architecture designed for a super-regenerative receiver (SR-RX) operated at the 400-MHz Medical Implantable Communications Service (MICS) band. The ΔΣ-PWD employs the operation principle of a ΔΣ modulator to convert the pulse-width (PW) value into digital domain and achieve fine resolution, which allows the SR-RX to support the 2-ASK/4-ASK modulations. It can be considered as the PW domain counterpart of a conventional ΔΣ modulator. The proposed architecture is capable of suppressing the PW quantization error over the direct-sampling-type PW detector by 23 dB. A linear model for the ΔΣ-PWD is devised in this paper for system analysis and design optimization. Fabricated in a 0.18-μm CMOS process, the whole receiver draws 700 μA from a 1.3-V supply, while the ΔΣ-PWD consumes only 100 μA. When operated on the 4-ASK modulation signal with 312-kbps data rate, the receiver achieves an energy efficiency of 2.9 nj/bit and -76-dBm sensitivity. View full abstract»

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  • A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS

    Publication Year: 2010 , Page(s): 2080 - 2090
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1184 KB) |  | HTML iconHTML  

    A 2.2 GS/s 4×-interleaved 6b ADC in 40 nm digital CMOS is presented. Each ADC slice consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic nonlinear amplifiers for low power consumption and high speed. The folding stage samples the input, removes its common-mode component and rectifies the differential voltage. The pipelined binary-search sub-ADC leverages threshold calibration to correct for amplifier and comparator imperfections, which allows the use of inherently nonlinear dynamic amplifiers. The prototype achieves 31.6 dB SNDR at 2.2 GS/s with a 2 GHz ERBW for 2.6 mW power consumption in an area of 0.03 mm2. View full abstract»

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  • A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors

    Publication Year: 2010 , Page(s): 2091 - 2103
    Cited by:  Papers (22)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (796 KB) |  | HTML iconHTML  

    An 11-bit 160-MS/s four-channel time-interleaved double-sampled pipelined ADC implemented in a 0.35-μm CMOS process is described. Digital calibration is used to correct mismatch errors between channels as well as the memory errors that arise from the use of double sampling. The signal-to-noise-and-distortion ratio is improved from 45 to 62 dB after calibration with an 8.7-MHz input. The spurious-free dynamic range is increased from 47 dB to 79 dB. View full abstract»

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  • A Low Phase-Noise Multi-Phase LO Generator for Wideband Demodulators Based on Reconfigurable Sub-Harmonic Mixers

    Publication Year: 2010 , Page(s): 2104 - 2115
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2231 KB) |  | HTML iconHTML  

    The advent of wideband systems, e.g., software defined radios, cognitive radios and UWB technology, motivates research for new transceiver architectures and circuit topologies to arrive at compact and low power solutions. Reference frequency generation in wideband CMOS receivers is usually power and area hungry. In this paper a wide band quadrature demodulator, based on mixers reconfigurable between fundamental and sub-harmonic operation modes is presented. The technique allows covering an RF bandwidth three times larger than the frequency covered by the synthesizer. Multiple local oscillator phases are required for the proposed architecture. For low phase noise and fast settling time, they are generated by means of a multi-stage injection locked ring oscillator. This solution proves very accurate and power efficient and may find applications in other communication systems requiring multiple phase references. A demodulator test chip tailored to WiMedia UWB groups 1, 3, 4 (3.1-9.5 GHz), and comprising mixers and frequency synthesizer, has been realized in a 65 nm CMOS technology. Experimental results show 10 dB of conversion gain with 2.3 nV/sqrt(Hz) equivalent input noise voltage spectral density. IIP2 and IIP3, with interferers in the GSM and WLAN bands, are 40 dBm and 11 dBm respectively. The synthesizer displays maximum spurs level of -43 dBc, a state of the art phase noise of -128 dBc/Hz@10 MHz offset and a settling time of less than 6 ns with 43 m W only. View full abstract»

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  • A 86 MHz–12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS

    Publication Year: 2010 , Page(s): 2116 - 2129
    Cited by:  Papers (25)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1790 KB) |  | HTML iconHTML  

    A 86 MHz-12 GHz digital-intensive reconfigurable PLL frequency synthesizer is presented with 100 kHz to 2 MHz bandwidth. It leverages a 6 fJ/step 5.5 ps, 14b coarse-fine TDC and a 6-12 GHz dual-VCO set. Several simple calibration schemes are proposed that enable the proper performance of the highly efficient TDC in the PLL. The 0.28 mm2 synthesizer, which is appropriate for use in a Software-Defined Radio, features noise cancellation and digital phase modulation and consumes less than 30 mW. View full abstract»

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  • Circuit Design and Modeling Techniques for Enhancing the Clock-Data Compensation Effect Under Resonant Supply Noise

    Publication Year: 2010 , Page(s): 2130 - 2141
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1916 KB) |  | HTML iconHTML  

    Recent publications have shown that clock jitter can improve timing margin through the compensation effect between the clock cycle and the datapath delay under the influence of resonant supply noise. This paper presents a comprehensive study of this beneficial clock-data compensation effect including an analysis of its dependency on various design parameters and a new phase-shifted clock buffer design that can enhance the effect. Measurement result from a 1.2 V, 65 nm test chip shows an 8-27% increase in the maximum operating frequency while saving 85% of the clock buffer area compared to prior art. An accurate timing model is derived to estimate the beneficial jitter effect. View full abstract»

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  • Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements

    Publication Year: 2010 , Page(s): 2142 - 2155
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2753 KB) |  | HTML iconHTML  

    Embedded NAND-type read-only-memory (NAND-ROM) provides large-capacity, high-reliability, on-chip non-volatile storage. However, NAND-ROM suffers from code-dependent read noises and cannot survive at low supply voltages (VDDs). These code-dependent read noises are primarily due to the charge-sharing effect, bitline leakage current, and crosstalk between bitlines, which become worse at lower VDD. This study proposes a dynamic split source-line (DSSL) scheme for NAND-ROM. The proposed scheme overcomes code-dependent read noises while improving the read access time and suppressing the active-mode gate leakage current, with only a 1% area penalty in the cell array. Experiments on a fabricated 256 Kb macro using a 90 nm industrial logic process demonstrate that the proposed DSSL scheme achieves 100% code-pattern coverage under a small sensing margin. Additionally, the DSSL NAND-ROM works with a wide range of supply voltages (1-0.31 V) with a 38%, 45.8%, and 37% improvement in speed, power, and standby current, respectively, at VDD = 1 V. View full abstract»

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  • Ferroelectric (Fe)-NAND Flash Memory With Batch Write Algorithm and Smart Data Store to the Nonvolatile Page Buffer for Data Center Application High-Speed and Highly Reliable Enterprise Solid-State Drives

    Publication Year: 2010 , Page(s): 2156 - 2164
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1705 KB) |  | HTML iconHTML  

    A ferroelectric (Fe)-NAND flash memory with a batch write algorithm and a smart data store to the nonvolatile page buffer is proposed. An enterprise solid-state drive (SSD) for a data center is a future promising market of NAND flash memories. The critical problem for such an enterprise SSD is a slow random write. The write unit in a NAND flash memory is a page, 4-8 KBytes. Because the minimum write unit of the operating system is a sector, 512 Bytes, a random write to write a smaller data than a page size frequently happens, which creates a garbage. As a garbage accumulates, a garbage collection is performed to increase a workable memory capacity. The garbage collection takes as much as 100 ms, which is 100 times longer than a page program time, 800 μs, and thus causes a serious performance degradation. In the proposed Fe-NAND flash memory, the data fragmentation in a random write is removed by introducing a batch write algorithm where a page buffer in the Fe-NAND flash memory temporarily stores a program data. The memory cell program starts after the program data as much as the page size accumulates in page buffers. As the data fragmentation is eliminated, the SSD performance can double. In addition, the nonvolatile page buffer realizes a power-outage-immune highly reliable operation. With a low program/erase voltage of 6 V and a high endurance of 100 million cycles, the proposed Fe-NAND flash memory is most suitable for a highly reliable highspeed low-power data-center-application enterprise SSD. View full abstract»

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  • Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control for High Program Inhibition in MLC NAND Flash Memories

    Publication Year: 2010 , Page(s): 2165 - 2172
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2202 KB) |  | HTML iconHTML  

    In this paper, dynamic Vpass ISPP schemes and optimizing Vth of erase memory cells are presented for achieving high program inhibition with lower program disturbance in sub-40 nm MLC NAND flash and beyond. Simple two-step dynamic Vpass control technique is used and over 40% program failure reduction after 30 k P/E cycling is achieved in the proposed scheme, compared to conventional method. A major pattern dependency of program disturbance in MLC NAND flash is also described in this paper. In order to achieve high immunity for the data pattern dependency in program disturbance, optimizing erase Vth and its distribution using ISPP-after-erase with a precise negative Vth sensing scheme are proposed. The proposed schemes are demonstrated using 42 nm MLC NAND flash test chip and about 2 times better Vpass window margin is obtained compared to conventional scheme. View full abstract»

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  • A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations

    Publication Year: 2010 , Page(s): 2173 - 2183
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1939 KB) |  | HTML iconHTML  

    This paper proposes a low-power SRAM using bit-line charge-recycling for read and write operations. The charge-recycling SRAM (CR-SRAM) reduces the read and write powers by recycling the charge in bit lines. When N bit lines recycle their charges, the swing voltage and power of bit lines are reduced to 1/N and 1/N2, respectively. The CR-SRAM utilizes hierarchical bit-line architecture to perform the charge-recycling without static noise margin degradation in memory cells. In the simulation, the CR-SRAM saves 17% read power and 84% write power compared with the conventional SRAM. A CR-SRAM chip with 4 K × 8 bits is implemented in a 0.13-μm CMOS process. It consumes 0.128-mW read power and 0.135-mW write power at fCLK = 100 MHz and VDD = 1.2 V. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan