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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 10 • Date Oct. 2010

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Displaying Results 1 - 18 of 18
  • Table of contents

    Publication Year: 2010, Page(s): C1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2010, Page(s): C2
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  • Fully CMOS-Compatible On-Chip Optical Clock Distribution and Recovery

    Publication Year: 2010, Page(s):1385 - 1398
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2252 KB) | HTML iconHTML

    Clock distribution in the multi-gigahertz range is getting increasingly difficult due to more stringent requirements for skew and jitter on one hand and the deteriorating supply voltage integrity and process variation on the other hand. Global clock network, especially in nanometer CMOS designs with ever increasing die sizes, has become a prominent performance limiter. A potential alternative to t... View full abstract»

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  • Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling

    Publication Year: 2010, Page(s):1399 - 1411
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1037 KB) | HTML iconHTML

    To efficiently analyze the large-scale interconnect dominant circuits with inductive couplings (mutual inductances), this paper introduces a new state matrix, called VNA, to stamp inverse-inductance elements by replacing inductive-branch current with flux. The state matrix under VNA is diagonal-dominant, sparse, and passive. To further explore the sparsity and hierarchy at the block level, a new m... View full abstract»

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  • Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding

    Publication Year: 2010, Page(s):1412 - 1420
    Cited by:  Papers (25)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1284 KB) | HTML iconHTML

    By storing more than one bit in each memory cell, multi-level per cell (MLC) NAND flash memories are dominating global flash memory market due to their appealing storage density advantage. However, continuous technology scaling makes MLC NAND flash memories increasingly subject to worse raw storage reliability. This paper presents a memory fault tolerance design solution geared to MLC NAND flash m... View full abstract»

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  • Stochastic Networked Computation

    Publication Year: 2010, Page(s):1421 - 1432
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3035 KB) | HTML iconHTML

    In this paper, the stochastic networked computation (SNC) paradigm for designing robust and energy-efficient systems-on-a-chip in nanoscale process technologies, where robust computation is treated as a statistical estimation problem is presented. The benefits of SNC are demonstrated by employing it to design an energy-efficient and robust pseudonoise-code acquisition system for the wireless CDMA2... View full abstract»

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  • A Fault-Tolerant Interconnect Mechanism for NMR Nanoarchitectures

    Publication Year: 2010, Page(s):1433 - 1446
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1708 KB) | HTML iconHTML

    Redundancy techniques, such as N -tuple modular redundancy (NMR), has been widely used to correct faulty behavior of components and achieve high reliability. Almost all redundancy-based strategies rely on a majority voting. The voter, therefore, becomes a critical unit for the correct operation of any NMR system. In this paper, we propose a voterless fault-tolerant strategy to implement a robust N... View full abstract»

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  • An Area-Efficient and Low-Power Multirate Decoder for Quasi-Cyclic Low-Density Parity-Check Codes

    Publication Year: 2010, Page(s):1447 - 1460
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2548 KB) | HTML iconHTML

    The quasi-cyclic low-density parity-check (QC-LDPC) codes are widely applied in digital broadcast and communication systems. However, the decoders are still difficult to be put into practice due to their large area and high power, especially in the wireless mobile devices. This paper presents an improved all-purpose multirate iterative decoder architecture for QC-LDPC codes, which can largely redu... View full abstract»

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  • Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing

    Publication Year: 2010, Page(s):1461 - 1470
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1648 KB) | HTML iconHTML

    In this paper, we present a novel discrete cosine transform (DCT) architecture that allows aggressive voltage scaling for low-power dissipation, even under process parameter variations with minimal overhead as opposed to existing techniques. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors appear only from the long paths that are designed to be less ... View full abstract»

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  • Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture

    Publication Year: 2010, Page(s):1471 - 1482
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2166 KB) | HTML iconHTML

    Coarse-grained reconfigurable architectures (CGRAs) aim to achieve both goals of high performance and flexibility. In addition, power consumption is significant for the reconfigurable architecture to be used as a competitive processing core in embedded systems. However, the existing reconfigurable architectures require too much area and power. In this paper, we propose a new design space explorati... View full abstract»

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  • Correlation-Based Rectangular Encoding

    Publication Year: 2010, Page(s):1483 - 1492
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB) | HTML iconHTML

    In this paper, a technique is presented for improving the compression achieved with any linear decompressor by adding a small nonlinear decoder that exploits bit-wise and pattern-wise correlations present in test vectors. The proposed nonlinear decoder has a regular and compact structure, and allows continuous-flow decompression. It has a very important feature, which is that its design does not d... View full abstract»

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  • Variable-Latency Floating-Point Multipliers for Low-Power Applications

    Publication Year: 2010, Page(s):1493 - 1497
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (455 KB) | HTML iconHTML

    This paper proposes a variable-latency floating-point multiplier architecture, which is compliant with IEEE 754-1985 and suitable for low-power applications. The architecture splits the significand multiplier into the upper and lower parts, and predicts the carry bit, sticky bit, and significand product from the upper part. In the case of correct prediction, the computation of lower part is disabl... View full abstract»

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  • Design and Implementation of a Sort-Free K-Best Sphere Decoder

    Publication Year: 2010, Page(s):1497 - 1501
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB) | HTML iconHTML

    This paper describes the design and very-large-scale integration (VLSI) architecture for a 4 × 4 breadth-first K-best multiple-input-multiple-output (MIMO) decoder using a 64 quadrature-amplitude modulation (QAM) scheme. A novel sort-free approach to path extension, as well as quantized metrics result in a high-throughput VLSI architecture with lower power and area consumption compared to s... View full abstract»

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  • Search for T-VLSI Editor-in-Chief

    Publication Year: 2010, Page(s): 1502
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    Publication Year: 2010, Page(s): 1503
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    Publication Year: 2010, Page(s): 1504
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2010, Page(s): C3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2010, Page(s): C4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu