IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 10 • Oct. 2010

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  • Table of contents

    Publication Year: 2010, Page(s):C1 - C4
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2010, Page(s): C2
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  • Guest Editorial

    Publication Year: 2010, Page(s):1457 - 1458
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  • High-Level Design and Validation of the BlueSPARC Multithreaded Processor

    Publication Year: 2010, Page(s):1459 - 1470
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (706 KB) | HTML iconHTML

    This paper presents our experiences in using high-level methods to design and validate a 16-way multithreaded microprocessor called BlueSPARC. BlueSPARC is an in-order, high-throughput processor supporting complex features such as privileged-mode operations, memory management, and a nonblocking cache subsystem. Using a high-level design language called Bluespec System Verilog (BSV), our final impl... View full abstract»

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  • Buffer Sharing in Rendezvous Programs

    Publication Year: 2010, Page(s):1471 - 1480
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (774 KB) | HTML iconHTML

    Most compilers focus on optimizing performance, often at the expense of memory, but efficient memory use can be just as important in constrained environments such as embedded systems. This paper presents a memory reduction technique for rendezvous communication, which is applied to the deterministic concurrent programming language SHIM. It focuses on reducing memory consumption by sharing communic... View full abstract»

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  • Combining Control and Data Abstraction in the Verification of Hybrid Systems

    Publication Year: 2010, Page(s):1481 - 1494
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1227 KB) | HTML iconHTML

    This paper addresses the verification of hybrid systems built as the composition of a discrete software controller interacting with a physical environment exhibiting a continuous behavior. The goal is to attack the problem of the combinatorial explosion of discrete states that may happen if a complex software controller is considered. It proposes as a solution to extend an existing abstract interp... View full abstract»

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  • Incremental and Verified Modeling of the PCI Express Protocol

    Publication Year: 2010, Page(s):1495 - 1508
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (438 KB) | HTML iconHTML

    PCI Express is a modern, high-performance communication protocol implementing sophisticated features to meet today's performance demands. Although an off-chip protocol, PCI Express implements many principles of future on-chip communication architectures. It is a highly complex protocol that is hard to verify formally. We present the application of a new approach to the PCI Express transaction and ... View full abstract»

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  • Exploring FPGA Routing Architecture Stochastically

    Publication Year: 2010, Page(s):1509 - 1522
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1928 KB) | HTML iconHTML

    This paper proposes a systematic strategy to efficiently explore the design space of field-programmable gate array (FPGA) routing architectures. The key idea is to use stochastic methods to quickly locate near-optimal solutions in designing FPGA routing architectures without exhaustively enumerating all design points. The main objective of this paper is not as much about the specific numerical res... View full abstract»

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  • Efficient Simulation of Power Grids

    Publication Year: 2010, Page(s):1523 - 1532
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (686 KB) | HTML iconHTML

    Modern deep sub-micron ultra-large scale integration designs with hundreds of millions of devices require huge grids for power distribution. Such grids, operating with decreasing power supply voltages, are a design limiting factor and accurate analysis of their behavior is of paramount importance as any voltage drops can seriously impact performance or functionality. As power grid models have mill... View full abstract»

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  • Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement

    Publication Year: 2010, Page(s):1533 - 1545
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (687 KB) | HTML iconHTML

    Starting from the 90 nm technology node, process induced stress has played a key role in the design of high-performance devices. The emergence of source/drain silicon germanium (S/D SiGe) technique as the most important stressing mechanism for p-channel metal-oxide-semiconductor field-effect transistor devices has opened up various optimization possibilities at circuit and physical design stage. I... View full abstract»

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  • Multicore Parallelization of Min-Cost Flow for CAD Applications

    Publication Year: 2010, Page(s):1546 - 1557
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1155 KB) | HTML iconHTML

    Computational complexity has been the primary challenge of many very large scale integration computer-aided design (CAD) applications. The emerging multicore and many-core microprocessors have the potential to offer scalable performance improvements. How to explore the multicore resources to speed up CAD applications is thus a natural question but also a huge challenge for CAD researchers. This pa... View full abstract»

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  • Power-Performance Analysis of Networks-on-Chip With Arbitrary Buffer Allocation Schemes

    Publication Year: 2010, Page(s):1558 - 1571
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1113 KB) | HTML iconHTML

    End-to-end delay, throughput, energy consumption, and silicon area are the most important design metrics of networks-on-chip (NoCs). Although several analytical models have been previously proposed for predicting such metrics in NoCs, very few of them consider the effect of message waiting time in the buffers of network routers for predicting overall power consumptions and none of them consider st... View full abstract»

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  • An SDRAM-Aware Router for Networks-on-Chip

    Publication Year: 2010, Page(s):1572 - 1585
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (801 KB) | HTML iconHTML

    Networks-on-chip (NoCs) may interface with lots of synchronous dynamic random access memories (SDRAM) to provide enough memory bandwidth and guaranteed quality-of-service for future systems-on-chip (SoCs). SDRAM is commonly controlled by a memory subsystem that schedules memory requests to improve memory efficiency and latency. However, a memory subsystem is still a performance bottleneck in the e... View full abstract»

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  • Accurate Direct and Indirect On-Chip Temperature Sensing for Efficient Dynamic Thermal Management

    Publication Year: 2010, Page(s):1586 - 1599
    Cited by:  Papers (50)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1135 KB) | HTML iconHTML

    Dynamic thermal management techniques require accurate runtime temperature information in order to operate effectively and efficiently. In this paper, we propose two novel solutions for accurate sensing of on-chip temperature. Our first technique is used at design time for sensor allocation and placement to minimize the number of sensors while maintaining the desired accuracy. The experimental res... View full abstract»

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  • An MILP-Based Performance Analysis Technique for Non-Preemptive Multitasking MPSoC

    Publication Year: 2010, Page(s):1600 - 1613
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1237 KB) | HTML iconHTML

    For real-time applications, it is necessary to estimate the worst-case performance early in the design process without actual hardware implementation. While the non-preemptive task scheduling is pertinent to multi-core platforms because of easy implementation and high performance, its scheduling anomaly behavior makes the worst-case performance estimation extremely difficult. In this paper, we pro... View full abstract»

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  • Multiple Transient Faults in Combinational and Sequential Circuits: A Systematic Approach

    Publication Year: 2010, Page(s):1614 - 1627
    Cited by:  Papers (48)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1239 KB) | HTML iconHTML

    Transient faults in logic circuits are becoming an important reliability concern for future technology nodes. Radiation-induced faults have received significant attention in recent years, while multiple transients originating from a single radiation hit are predicted to occur more often. Furthermore, some effects, like reconvergent fanout-induced glitches, are more pronounced in the case of multip... View full abstract»

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  • DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs

    Publication Year: 2010, Page(s):1628 - 1639
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1327 KB) | HTML iconHTML

    Built-in self-repair (BISR) techniques are widely used to enhance the yield of embedded random access memories (RAMs). Fault-location ability of test algorithms executed by a BISR circuit has heavy impact on the repair efficiency of the BISR circuit. This paper proposes a defect-aware BISR (DABISR) scheme for single-port RAMs (SPRAMs) and multi-port RAMs (MPRAMs) in system chips. Multiple RAMs can... View full abstract»

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  • Single and Variable-State-Skip LFSRs: Bridging the Gap Between Test Data Compression and Test Set Embedding for IP Cores

    Publication Year: 2010, Page(s):1640 - 1644
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (569 KB) | HTML iconHTML

    Even though test set embedding (TSE) methods offer very high compression efficiency, their excessively long test application times prohibit their use for testing systems-on-chip (SoC). To alleviate this problem we present two new types of linear feedback shift registers (LFSRs), the Single-State-Skip and the Variable-State-Skip LFSRs. Both are normal LFSRs with the addition of the State-Skip circu... View full abstract»

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  • SOC Test Architecture and Method for 3-D ICs

    Publication Year: 2010, Page(s):1645 - 1649
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (567 KB) | HTML iconHTML

    3-D integration provides another way to put more devices in a smaller footprint. However, it also introduces new challenges in testing. Flexible test architecture named test access control system for 3-D integrated circuits (TACS-3D) is proposed for 3-D integrated circuits (IC) testing. Integration of heterogeneous design-for-testability methods for logic, memory, and through-silicon via (TSV) tes... View full abstract»

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  • Interconnect Bundle Sizing Under Discrete Design Rules

    Publication Year: 2010, Page(s):1650 - 1654
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB) | HTML iconHTML

    The lithography used for 32 nm and smaller very large scale integrated process technologies restricts the admissible interconnect widths and spaces to a small set of discrete values with some interdependencies, so that traditional interconnect sizing by continuous-variable optimization techniques becomes impossible. We present a dynamic programming (DP) algorithm for simultaneous sizing and spacin... View full abstract»

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  • Formal Analysis of End-Around-Carry Adder in Floating-Point Unit

    Publication Year: 2010, Page(s):1655 - 1659
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (309 KB) | HTML iconHTML

    End-around-carry (EAC) adder is extensively used in microprocessor's floating-point units. This paper presents an algebraic characterization of an EAC adder's algorithm. A novel symbolic analysis approach is presented to prove the EAC adder's correctness. Algebraic structures and first-order recursive equations are harnessed in proof derivations. A hybrid prefix/EAC architecture is considered. View full abstract»

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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2010, Page(s): 1660
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2010, Page(s): C3
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu