# IEEE Transactions on Electron Devices

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Displaying Results 1 - 25 of 61

Publication Year: 2010, Page(s):C1 - 2362
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2010, Page(s): C2
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• ### Physics, Technology, and Modeling of Complementary Asymmetric MOSFETs

Publication Year: 2010, Page(s):2363 - 2380
Cited by:  Papers (8)
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The physics, technology, and modeling of complementary asymmetric MOSFETs are reviewed and illustrated with statistically representative silicon data from a recent manufacturing implementation, in which the transistors for the secondary power supply voltage are offered in asymmetric and symmetric constructions. The in-depth analysis of the device physics of asymmetric transistors provides new insi... View full abstract»

• ### Self-Aligned Amorphous Silicon Thin-Film Transistors Fabricated on Clear Plastic at 300 $^{circ}hbox{C}$

Publication Year: 2010, Page(s):2381 - 2389
Cited by:  Papers (9)
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We fabricated back-channel-cut and back-channel-passivated hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) on clear-plastic (CP) foil substrates using a silicon nitride (SiN∞) deposition temperature of 300°C. The TFTs were fabricated on CP and are as stable under high gate bias as TFTs made on glass substrates. A self-alignment technique was developed ... View full abstract»

• ### A Deterministic Boltzmann Equation Solver Based on a Higher Order Spherical Harmonics Expansion With Full-Band Effects

Publication Year: 2010, Page(s):2390 - 2397
Cited by:  Papers (7)
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In this paper, a deterministic Boltzmann equation solver based on a higher order spherical harmonics expansion, including full-band (FB) effects, is presented. An anisotropic band structure for the conduction band with an invertible energy/wave vector relation has been generated by matching several moments of the group velocity of the silicon FB structure. A generalized formulation of the free-str... View full abstract»

• ### A New Class of Charge-Trap Flash Memory With Resistive Switching Mechanisms

Publication Year: 2010, Page(s):2398 - 2404
Cited by:  Papers (9)
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This paper presents a new class of charge-trap Flash memory device with resistive switching mechanisms. We propose a fused memory scheme using a structure of metal/Pr0.7Ca0.3MnO3 (PCMO)/nitride/oxide/silicon to graft fast-switching features of resistive random access memory onto high-density silicon/oxide/nitride/oxide/silicon memory structures. In this scheme, bot... View full abstract»

• ### Analytic Model for the Surface Potential and Drain Current in Negative Capacitance Field-Effect Transistors

Publication Year: 2010, Page(s):2405 - 2409
Cited by:  Papers (54)
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In 2008, Salahuddin and Datta proposed that a ferroelectric material operating in the negative capacitance (NC) region could act as a step-up converter of the surface potential in a metal-oxide-semiconductor structure, opening a new route for the realization of transistors with steeper subthreshold characteristics (S <; 60mV/dec). In this paper, a comprehensive physics-based surface potential a... View full abstract»

• ### Dual-$k$ Spacer Device Architecture for the Improvement of Performance of Silicon n-Channel Tunnel FETs

Publication Year: 2010, Page(s):2410 - 2417
Cited by:  Papers (38)
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A dual-k spacer concept is proposed and evaluated in underlap and nonunderlap n-channel silicon tunnel field-effect transistors (FETs) for the first time using extensive device simulations. The dual-k spacer consists of an inner layer made of a high-k material and an outer layer made of a low-k material. It is shown that the dual-k spacer improves the performance of n-channel tunneling FETs and mo... View full abstract»

• ### Hierarchical Simulation of Statistical Variability: From 3-D MC With “ ab initio” Ionized Impurity Scattering to Statistical Compact Models

Publication Year: 2010, Page(s):2418 - 2426
Cited by:  Papers (11)
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Quantum corrections based on density gradient formalism, recently introduced in the 3-D Monte Carlo (MC) module of the Glasgow “atomistic” simulator, are used to simultaneously capture quantum confinement effects as well as “ab initio” ionized impurity scattering. This has allowed us to consistently study the impact of transport variability due to scattering from random... View full abstract»

• ### Shape Effect of Silicon Nitride Subwavelength Structure on Reflectance for Silicon Solar Cells

Publication Year: 2010, Page(s):2427 - 2433
Cited by:  Papers (18)  |  Patents (1)
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In this paper, we, for the first time, examine the spectral reflectivity of hemisphere-, cone-, cylinder-, and parabola-shaped silicon nitride (Si3N4) subwavelength structures (SWSs). A multilayer rigorous coupled-wave approach is advanced to evaluate the reflection properties of Si3N4 SWSs. We optimize the aforementioned four different shapes of SWSs in... View full abstract»

• ### Intrinsic Gain in Self-Aligned Polysilicon Source-Gated Transistors

Publication Year: 2010, Page(s):2434 - 2439
Cited by:  Papers (18)
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Thin-film self-aligned source-gated transistors (SGTs) have been made in polysilicon. The very high output impedance of this type of transistor makes it suited to analog circuits. Intrinsic voltage gains of greater than 1000 have been measured at particular drain voltages. The drain voltage dependence of the gain is explained based on the device physics of the SGT and the fact that a pinchoff occu... View full abstract»

• ### Channel Length and Threshold Voltage Dependence of Transistor Mismatch in a 32-nm HKMG Technology

Publication Year: 2010, Page(s):2440 - 2447
Cited by:  Papers (12)  |  Patents (1)
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In this paper, it is shown empirically and through simulation that transistor mismatch due to random dopant fluctuation is a function of the well and halo design of the transistor, and that, contrary to conventional expectation, low-threshold transistors can have larger mismatch than higher threshold transistors. The complex dependence of mismatch on well and halo profiles suggests the need for th... View full abstract»

• ### Electronic Transport in Laterally Asymmetric Channel MOSFET for RF Analog Applications

Publication Year: 2010, Page(s):2448 - 2454
Cited by:  Papers (9)
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In this paper, an ensemble Monte Carlo investigation of the static and dynamic performances in the high-frequency domain of laterally asymmetric channel (LAC) bulk metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented. A detailed comparison with a homogeneously doped bulk device is also included. The results presented show that the use of an asymmetric doping within the channel... View full abstract»

• ### A Direct Method for Charge Collection Probability Computation Using the Reciprocity Theorem

Publication Year: 2010, Page(s):2455 - 2461
Cited by:  Papers (2)
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This paper presents a simple and direct method for computing the charge collection probability distribution by utilizing the reciprocity theorem. The proposed method simplifies the charge collection probability computation with the use of the finite difference method. We demonstrate the method by computing the charge collection probability distribution of two finite junction configurations, the L-... View full abstract»

• ### 20% Efficient Screen-Printed Cells With Spin-On-Dielectric-Passivated Boron Back-Surface Field

Publication Year: 2010, Page(s):2462 - 2469
Cited by:  Papers (7)
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This paper reports on the characteristics of a spin-on dielectric which has been used as the rear-surface passivation layer to achieve 20% efficient screen-printed (SP) boron back-surface field (B-BSF) solar cells. The dielectric provides, in a single thermal step, both stable passivation of a heavily doped p+ surface and strong gettering of iron which is a common contaminant in high-te... View full abstract»

• ### Avalanche Breakdown Delay in ESD Protection Diodes

Publication Year: 2010, Page(s):2470 - 2476
Cited by:  Papers (5)
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Electrostatic discharge (ESD) protection diodes with a breakdown (BD) voltage above 50 V might exhibit a BD delay in the order of microseconds. The phenomenon is related to the low generation of seed carriers that can start an avalanche BD event by impact ionization. However, emission of carriers from deep traps, or the onset of tunneling generation, can shorten the delay to only fractions of a na... View full abstract»

• ### A Model of the Gate Capacitance of Surrounding Gate Transistors: Comparison With Double-Gate MOSFETs

Publication Year: 2010, Page(s):2477 - 2483
Cited by:  Papers (6)
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In this work, we develop a comprehensive model of the total gate capacitance (CG) of circular-cross-section surrounding gate transistors that accounts for both the insulator gate capacitance (Cins) and the inversion capacitance (Cinv). The accuracy of the model is checked with the results obtained from the numerical simulation of the structure. Using this model, we... View full abstract»

• ### A New Multipulse Technique for Probing Electron Trap Energy Distribution in High- $kappa$ Materials for Flash Memory Application

Publication Year: 2010, Page(s):2484 - 2492
Cited by:  Papers (17)
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A new discharge-based multipulse technique has been developed in this paper, which overcomes the shortcomings of the existing techniques, such as the charge pumping, charge injection and sensing, and two-pulse C-V techniques. It captures the energy signature for electron traps across high-κ materials and can be a useful tool for material selection during technology development. Trap distrib... View full abstract»

• ### Physical Origins of Threshold Voltage Variation Enhancement in Si(110) n/pMOSFETs

Publication Year: 2010, Page(s):2493 - 2498
Cited by:  Papers (2)
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Threshold voltage Vth variations in scaled (110) n/pMOSFETs are systematically investigated. Vth variations in (110) nMOSFETs and pMOSFETs with high channel dose are larger than those in (100) nMOSFETs and pMOSFETs, respectively. Physical origins of Vth variation enhancement in (110) MOSFETs are analyzed on the basis of the substrate impurity concentration dependen... View full abstract»

• ### Transient Simulation to Analyze Flash Memory Erase Improvements Due to Germanium Content in the Substrate

Publication Year: 2010, Page(s):2499 - 2503
Cited by:  Papers (8)
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We present a detailed and accurate physics-based transient simulation for modeling Flash memory erase characteristics when the substrate contains different percentages of germanium (Ge). Typical cells are erased by moving electrons from the floating gate to the drain, source, or substrate. This paper addresses substrate erase modeling using a simulation based on the solution to Poisson's equation ... View full abstract»

• ### Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part I: Modeling, Analysis, and Experimental Validation

Publication Year: 2010, Page(s):2504 - 2514
Cited by:  Papers (64)
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This paper highlights and experimentally verifies a new source of random threshold-voltage (V_th) fluctuation in emerging metal-gate transistors and proposes a statistical framework to investigate its device and circuit-level implications. The new source of variability, christened work-function (WF) variation (WFV), is caused by the dependence of metal WF on the orientation of its grains. The expe... View full abstract»

• ### Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part II: Implications for Process, Device, and Circuit Design

Publication Year: 2010, Page(s):2515 - 2525
Cited by:  Papers (36)
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This paper investigates the process, device, and circuit design implications of grain-orientation-induced work function variation (WFV) in high-k/metal-gate devices. WFV is caused by the dependence of the work function of metal grains on their orientations and is analytically modeled in the companion paper (part I). Using this modeling framework, various implications of WFV are investigated in thi... View full abstract»

• ### Insulating Halos to Boost Planar NMOSFET Performance

Publication Year: 2010, Page(s):2526 - 2530
Cited by:  Patents (1)
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Short-channel controllability by insulating halo (IH) is investigated using the NFET strained-Si technology. By embedding SiO2/Si3N4 insulators in the halo regions, the increase of halo implant concentration reduces source/drain depths and improves short-channel effects such as drain-induced barrier lowering. With Ioff similar to the control device at th... View full abstract»

• ### Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies

Publication Year: 2010, Page(s):2531 - 2538
Cited by:  Papers (147)  |  Patents (5)
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Cross-point memory architecture offers high device density, yet it suffers from substantial sneak path leakages, which result in large power dissipation and a small sensing margin. The parasitic resistance associated with the interconnects further degrades the output signal and imposes an additional limitation on the maximum allowable array size. In this paper, we study the device requirements of ... View full abstract»

• ### Electrical TCAD Simulations of a Germanium pMOSFET Technology

Publication Year: 2010, Page(s):2539 - 2546
Cited by:  Papers (47)
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A commercial technology computer-aided design device simulator was extended to allow electrical simulations of sub-100-nm germanium pMOSFETs. Parameters for generation/recombination mechanisms (Shockley-Read-Hall, trap-assisted tunneling, and band-to-band tunneling) and mobility models (impurity scattering and mobility reduction at high lateral and transversal field) are provided. The simulations ... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy