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Electron Devices, IEEE Transactions on

Issue 10 • Date Oct. 2010

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Displaying Results 1 - 25 of 61
  • Table of contents

    Page(s): C1 - 2362
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  • IEEE Transactions on Electron Devices publication information

    Page(s): C2
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  • Physics, Technology, and Modeling of Complementary Asymmetric MOSFETs

    Page(s): 2363 - 2380
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2186 KB) |  | HTML iconHTML  

    The physics, technology, and modeling of complementary asymmetric MOSFETs are reviewed and illustrated with statistically representative silicon data from a recent manufacturing implementation, in which the transistors for the secondary power supply voltage are offered in asymmetric and symmetric constructions. The in-depth analysis of the device physics of asymmetric transistors provides new insights into their physical operation and into the operation of transistors using halo implants in general. The variability, matching, and noise implications of using halo implants are also analyzed, concluding that both asymmetric and symmetric devices need to be offered for uncompromised circuit design. The challenges associated with the compact modeling the asymmetric transistors are also reviewed and illustrated. The preferred manufacturing implementation uses retrograde wells with no dopant fillers at the surface, while avoiding the drain-to-source punch-through by source-side-only halo implants. In addition to the known switching speed and maximum voltage gain advantages of the asymmetric transistors, this particular device architecture offers superior hot-carrier reliability and transistor design flexibility. The availability of retrograde wells enables construction of high-reliability complementary extended-drain MOSFETs for a third higher power supply voltage. View full abstract»

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  • Self-Aligned Amorphous Silicon Thin-Film Transistors Fabricated on Clear Plastic at 300 ^{\circ}\hbox {C}

    Page(s): 2381 - 2389
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    We fabricated back-channel-cut and back-channel-passivated hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) on clear-plastic (CP) foil substrates using a silicon nitride (SiN) deposition temperature of 300°C. The TFTs were fabricated on CP and are as stable under high gate bias as TFTs made on glass substrates. A self-alignment technique was developed to align the channel passivation, the a-Si:H island, and the source/drain (S/D) terminals to the gate. Self-alignment allowed us to fabricate discrete TFTs across 7 7 × cm2 of a free-standing sheet of CP foil to reduce the TFT channel length L to 3 m and reduce the S/D overlap with the gate LSD to ~1. To test the self-alignment techniques, we fabricated ring oscillators on the CP substrates. These results show that it is possible to fabricate state-of-the-art self-aligned a-Si:H TFTs and TFT circuits on plastic substrates. View full abstract»

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  • A Deterministic Boltzmann Equation Solver Based on a Higher Order Spherical Harmonics Expansion With Full-Band Effects

    Page(s): 2390 - 2397
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    In this paper, a deterministic Boltzmann equation solver based on a higher order spherical harmonics expansion, including full-band (FB) effects, is presented. An anisotropic band structure for the conduction band with an invertible energy/wave vector relation has been generated by matching several moments of the group velocity of the silicon FB structure. A generalized formulation of the free-streaming operator is presented, which is stabilized according to the maximum entropy dissipation scheme. From the numerical results for various systems such as silicon bulk, an n+-n-n+ structure, and SiGe heterojunction bipolar transistors, it can be concluded that the new model improves significantly the accuracy of the Boltzmann solver compared to previous band models without degrading the numerical stability. View full abstract»

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  • A New Class of Charge-Trap Flash Memory With Resistive Switching Mechanisms

    Page(s): 2398 - 2404
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    This paper presents a new class of charge-trap Flash memory device with resistive switching mechanisms. We propose a fused memory scheme using a structure of metal/Pr0.7Ca0.3MnO3 (PCMO)/nitride/oxide/silicon to graft fast-switching features of resistive random access memory onto high-density silicon/oxide/nitride/oxide/silicon memory structures. In this scheme, both program and erase (P/E) are performed by the conduction of the carriers that are injected from the gate into the nitride layer through the PCMO, which is a resistive switching material; the resistance state determines whether a program or erase function is performed. In the proposed memory devices, we observed improved memory characteristics, including the current-voltage hysteresis having a resistive ratio exceeding three orders of magnitude at a set voltage of 4.5 V, a memory window of 2.3 V, a P/E speed of 100 ns/1 ms, data retention of ten years, and endurance of 105 P/E cycles. This approach will offer critical clues about how one can best implement universal features of nonvolatile memories in a single chip. View full abstract»

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  • Analytic Model for the Surface Potential and Drain Current in Negative Capacitance Field-Effect Transistors

    Page(s): 2405 - 2409
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    In 2008, Salahuddin and Datta proposed that a ferroelectric material operating in the negative capacitance (NC) region could act as a step-up converter of the surface potential in a metal-oxide-semiconductor structure, opening a new route for the realization of transistors with steeper subthreshold characteristics (S <; 60mV/dec). In this paper, a comprehensive physics-based surface potential and a drain current model for the NC field-effect transistor are reported. The model is aimed to evaluate the potentiality of such transistors for low-power switching applications. This paper also sheds light on how operation in the NC region can be experimentally detected. View full abstract»

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  • Dual- k Spacer Device Architecture for the Improvement of Performance of Silicon n-Channel Tunnel FETs

    Page(s): 2410 - 2417
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    A dual-k spacer concept is proposed and evaluated in underlap and nonunderlap n-channel silicon tunnel field-effect transistors (FETs) for the first time using extensive device simulations. The dual-k spacer consists of an inner layer made of a high-k material and an outer layer made of a low-k material. It is shown that the dual-k spacer improves the performance of n-channel tunneling FETs and more so for the underlap structures. Performance improvements are illustrated and explained for SiO2, Al2O3, and HfO2 gate dielectrics. The structure is optimized for the on-state current without degrading the off-state current or the subthreshold slope. View full abstract»

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  • Hierarchical Simulation of Statistical Variability: From 3-D MC With “ ab initio” Ionized Impurity Scattering to Statistical Compact Models

    Page(s): 2418 - 2426
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    Quantum corrections based on density gradient formalism, recently introduced in the 3-D Monte Carlo (MC) module of the Glasgow “atomistic” simulator, are used to simultaneously capture quantum confinement effects as well as “ab initio” ionized impurity scattering. This has allowed us to consistently study the impact of transport variability due to scattering from random discrete dopants on the on-current variability in realistic nano-CMOS transistors. Such simulations result in an increased drain current variability when compared with the drift diffusion (DD) simulation. For the first time, a method that is used to accurately transfer the increased on-current variability obtained from the “ ab initio” MC simulations to the DD simulations is subsequently presented. The MC-corrected DD simulations are used to produce the target I-V characteristics from which the statistical compact models are extracted for use in preliminary design kits at the early stage of new technology development. View full abstract»

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  • Shape Effect of Silicon Nitride Subwavelength Structure on Reflectance for Silicon Solar Cells

    Page(s): 2427 - 2433
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (622 KB) |  | HTML iconHTML  

    In this paper, we, for the first time, examine the spectral reflectivity of hemisphere-, cone-, cylinder-, and parabola-shaped silicon nitride (Si3N4) subwavelength structures (SWSs). A multilayer rigorous coupled-wave approach is advanced to evaluate the reflection properties of Si3N4 SWSs. We optimize the aforementioned four different shapes of SWSs in terms of effective reflectance over a range of wavelength. The results of our paper show that a lowest effective reflectivity could be achieved for the optimized cone-shaped SWS as compared to hemisphere-, parabola-, and cylinder-shaped structures with the same volume. The best shape SWS is then fabricated together with a silicon (Si) solar cell, and the efficiency of the solar cell is compared with that of a solar cell with single-layer antireflection coating (ARC). An increase of 1.09% in cell efficiency () is observed for the Si solar cell with a cone-shaped Si3N4 SWS (12.86%) as compared with the cell with single-layer Si3N4 ARCs (11.77%). View full abstract»

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  • Intrinsic Gain in Self-Aligned Polysilicon Source-Gated Transistors

    Page(s): 2434 - 2439
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (361 KB) |  | HTML iconHTML  

    Thin-film self-aligned source-gated transistors (SGTs) have been made in polysilicon. The very high output impedance of this type of transistor makes it suited to analog circuits. Intrinsic voltage gains of greater than 1000 have been measured at particular drain voltages. The drain voltage dependence of the gain is explained based on the device physics of the SGT and the fact that a pinchoff occurs at both the source and the drain. The results obtained from these devices, which are far from optimal, suggest that, with a proper design, the SGT is well suited to a wide range of analog applications. View full abstract»

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  • Channel Length and Threshold Voltage Dependence of Transistor Mismatch in a 32-nm HKMG Technology

    Page(s): 2440 - 2447
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (324 KB) |  | HTML iconHTML  

    In this paper, it is shown empirically and through simulation that transistor mismatch due to random dopant fluctuation is a function of the well and halo design of the transistor, and that, contrary to conventional expectation, low-threshold transistors can have larger mismatch than higher threshold transistors. The complex dependence of mismatch on well and halo profiles suggests the need for the extension of the conventional Pelgrom approach to characterizing mismatch for a given technology and also suggests means of optimizing mismatch for analog applications. A set of screening criteria for mismatch data analysis are presented to verify that conclusions drawn from the standard deviation of a distribution may be properly applied. View full abstract»

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  • Electronic Transport in Laterally Asymmetric Channel MOSFET for RF Analog Applications

    Page(s): 2448 - 2454
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (457 KB) |  | HTML iconHTML  

    In this paper, an ensemble Monte Carlo investigation of the static and dynamic performances in the high-frequency domain of laterally asymmetric channel (LAC) bulk metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented. A detailed comparison with a homogeneously doped bulk device is also included. The results presented show that the use of an asymmetric doping within the channel enhances nonequilibrium features as velocity overshoot, thus significantly improving the transconductance of the device. The gradual variation of doping is also responsible for a modification of the electrostatic conditions and the inversion charge profiles, provoking the reduction of the gate-to-source capacitance, a minor influence of surface scattering, reduced transit times, and higher mean free paths. A noticeable enhancement (as compared to a conventional device) in the RF and microwave frequency range of the dynamic performance of the transistors is also evidenced. This is mainly due to a better transconductance-to-current ratio, Early voltage, and open-loop gain, which are the results of the improvement of the charge transport conditions in the device at a microscopic level. Therefore, LAC MOSFETs can be a viable option to enhance the figures of merit of bulk silicon technology for high-frequency analog applications. View full abstract»

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  • A Direct Method for Charge Collection Probability Computation Using the Reciprocity Theorem

    Page(s): 2455 - 2461
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (578 KB) |  | HTML iconHTML  

    This paper presents a simple and direct method for computing the charge collection probability distribution by utilizing the reciprocity theorem. The proposed method simplifies the charge collection probability computation with the use of the finite difference method. We demonstrate the method by computing the charge collection probability distribution of two finite junction configurations, the L-shaped and the U-shaped junction wells, and comparing the computational results with that obtained from the analytical expression as well as with the experiment. Good agreements were found. This method has the potential of advancing our understanding of photovoltaic devices as well as semiconductor characterization techniques, which make use of the charge collection process. View full abstract»

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  • 20% Efficient Screen-Printed Cells With Spin-On-Dielectric-Passivated Boron Back-Surface Field

    Page(s): 2462 - 2469
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (899 KB) |  | HTML iconHTML  

    This paper reports on the characteristics of a spin-on dielectric which has been used as the rear-surface passivation layer to achieve 20% efficient screen-printed (SP) boron back-surface field (B-BSF) solar cells. The dielectric provides, in a single thermal step, both stable passivation of a heavily doped p+ surface and strong gettering of iron which is a common contaminant in high-temperature boron diffusion processes. It was found that gettering of silicon substrates, contaminated during boron diffusion, is most effective when the dielectric is deposited on top of the boron-doped layer. The effect of dielectric charge density on passivation of p+ surfaces was also studied and a very high charge density of -1013 cm-2 was found to be necessary to significantly improve the passivation on surfaces with a boron concentration. View full abstract»

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  • Avalanche Breakdown Delay in ESD Protection Diodes

    Page(s): 2470 - 2476
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (765 KB) |  | HTML iconHTML  

    Electrostatic discharge (ESD) protection diodes with a breakdown (BD) voltage above 50 V might exhibit a BD delay in the order of microseconds. The phenomenon is related to the low generation of seed carriers that can start an avalanche BD event by impact ionization. However, emission of carriers from deep traps, or the onset of tunneling generation, can shorten the delay to only fractions of a nanosecond. Emission from deep traps has been found strong enough to make this kind of device effective for protection under standard ESD conditions. However, the application of a bias voltage prior to a stress pulse empties the trap states and thus leads to increasing BD delay. This paper investigates the BD delay in an ESD protection diode under various bias and pulse conditions. A model for the BD delay is proposed, taking into account the different seed carrier generation mechanisms. The activation energy of the dominating deep trap can be calculated to 0.18 eV by measuring the time to BD at different temperatures. View full abstract»

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  • A Model of the Gate Capacitance of Surrounding Gate Transistors: Comparison With Double-Gate MOSFETs

    Page(s): 2477 - 2483
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (411 KB) |  | HTML iconHTML  

    In this work, we develop a comprehensive model of the total gate capacitance (CG) of circular-cross-section surrounding gate transistors that accounts for both the insulator gate capacitance (Cins) and the inversion capacitance (Cinv). The accuracy of the model is checked with the results obtained from the numerical simulation of the structure. Using this model, we compare the CG/Cins ratio with that of double-gate (DG) transistors and study the degradation of the total gate capacitance of both devices as a function of the gate voltage and device size. It is shown that the CG/Cins ratio is higher in DGs, particularly for very small devices. View full abstract»

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  • A New Multipulse Technique for Probing Electron Trap Energy Distribution in High- \kappa Materials for Flash Memory Application

    Page(s): 2484 - 2492
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    A new discharge-based multipulse technique has been developed in this paper, which overcomes the shortcomings of the existing techniques, such as the charge pumping, charge injection and sensing, and two-pulse C-V techniques. It captures the energy signature for electron traps across high-κ materials and can be a useful tool for material selection during technology development. Trap distributions in HfO2, AI2O3, and HfAlO have been compared to identify the effects of material variation. It is observed that hafnium gives the shallow traps at about 0.45 eV above the silicon conduction band bottom (Si ECB), and the deep traps at 0.8 eV below the Si ECB are caused by aluminum. HfO2 combines the features in HfO2 and AI2O3. A peak near the Si ECB has been observed in all the three materials. View full abstract»

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  • Physical Origins of Threshold Voltage Variation Enhancement in Si(110) n/pMOSFETs

    Page(s): 2493 - 2498
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB) |  | HTML iconHTML  

    Threshold voltage Vth variations in scaled (110) n/pMOSFETs are systematically investigated. Vth variations in (110) nMOSFETs and pMOSFETs with high channel dose are larger than those in (100) nMOSFETs and pMOSFETs, respectively. Physical origins of Vth variation enhancement in (110) MOSFETs are analyzed on the basis of the substrate impurity concentration dependence of the body effect and S factor variations. It is found that the depletion width variations due to boron ion channeling and the interface trap density variations enhance Vth variations in boron-doped (110) nMOSFETs and that the interface fixed charge variations enhance Vth variations in arsenic-doped (110) pMOSFETs. An undoped channel combined with a steep boron profile and moderate phosphorus doping into the surface are desirable to minimize Vth variations in (110) nMOSFETs and pMOSFETs, respectively. View full abstract»

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  • Transient Simulation to Analyze Flash Memory Erase Improvements Due to Germanium Content in the Substrate

    Page(s): 2499 - 2503
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB) |  | HTML iconHTML  

    We present a detailed and accurate physics-based transient simulation for modeling Flash memory erase characteristics when the substrate contains different percentages of germanium (Ge). Typical cells are erased by moving electrons from the floating gate to the drain, source, or substrate. This paper addresses substrate erase modeling using a simulation based on the solution to Poisson's equation with Ge percentage as an independent variable. The goal of this paper is to demonstrate the derivation of an accurate erase simulation and show the improvements that can be achieved by using silicon-germanium (SiGe) substrate material versus silicon (Si) only. Several papers have been published on MOSFETs with SiGe substrates, but none has been published on the use of SiGe substrates in Flash memory. View full abstract»

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  • Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part I: Modeling, Analysis, and Experimental Validation

    Page(s): 2504 - 2514
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    This paper highlights and experimentally verifies a new source of random threshold-voltage (V_th) fluctuation in emerging metal-gate transistors and proposes a statistical framework to investigate its device and circuit-level implications. The new source of variability, christened work-function (WF) variation (WFV), is caused by the dependence of metal WF on the orientation of its grains. The experimentally measured data reported in this paper confirm the existence of such variations in both planar and nonplanar high-k metal-gate transistors. As a result of WFV, the WFs of metal gates are statistical distributions instead of deterministic values. In this paper, the key parameters of such WF distributions are analytically modeled by identifying the physical dimensions of the devices and properties of materials used in the fabrication. It is shown that WFV can be modeled by a multinomial distribution where the key parameters of its probability distribution function can be calculated in terms of the aforementioned parameters. The analysis reveals that WFV will contribute a key source of V_th variability in emerging generations of metal-gate devices. Using the proposed framework, one can investigate the implications of WFV for process, device, and circuit design, which are discussed in Part II. View full abstract»

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  • Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part II: Implications for Process, Device, and Circuit Design

    Page(s): 2515 - 2525
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (752 KB) |  | HTML iconHTML  

    This paper investigates the process, device, and circuit design implications of grain-orientation-induced work function variation (WFV) in high-k/metal-gate devices. WFV is caused by the dependence of the work function of metal grains on their orientations and is analytically modeled in the companion paper (part I). Using this modeling framework, various implications of WFV are investigated in this paper. It is shown that process designers can utilize the proposed models to reduce the impact of WFV by identifying proper materials and fabrication processes. For instance, four types of metal nitride gate materials (TiN and TaN for NMOS devices and WN and MoN for PMOS devices) are studied, and it is shown that TiN and WN result in lower V_th fluctuations. Moreover, device engineers can study the impact of WFV on various types of classical and nonclassical metal-gate CMOS transistors using these analytical models. As an example, it is shown that, for a given channel length, single-fin FinFETs are less affected by WFV compared to fully depleted SOI and bulk-Si devices due to their larger gate area. Furthermore, circuit designers can benefit from the proposed modeling framework that allows straightforward evaluation of the key performance and reliability parameters of the circuits under such V_th fluctuations. For instance, an SRAM cell is analyzed in the presence of V_th fluctuations due to WFV, and it is shown that such variations can result in considerable performance and reliability degradation. View full abstract»

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  • Insulating Halos to Boost Planar NMOSFET Performance

    Page(s): 2526 - 2530
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    Short-channel controllability by insulating halo (IH) is investigated using the NFET strained-Si technology. By embedding SiO2/Si3N4 insulators in the halo regions, the increase of halo implant concentration reduces source/drain depths and improves short-channel effects such as drain-induced barrier lowering. With Ioff similar to the control device at the same gate length by adjusting the threshold voltage, the channel doping can be reduced, and the channel mobility increases due to the decrease of vertical electric field. Moreover, IHs reduce the shallow trench isolation compressive stress in the channel and yield a high-electron mobility enhancement. The device performance is optimized based on the simulation design. Up to a 23% Ion improvement was experimentally achieved by optimal IH insertion. A 7% lower junction capacitance and an 8% ring oscillator speed improvement are demonstrated when the IH is adopted in the NFET alone. Moreover, device reliability is carefully examined and is not adversely impacted by IH insertion. View full abstract»

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  • Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies

    Page(s): 2531 - 2538
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    Cross-point memory architecture offers high device density, yet it suffers from substantial sneak path leakages, which result in large power dissipation and a small sensing margin. The parasitic resistance associated with the interconnects further degrades the output signal and imposes an additional limitation on the maximum allowable array size. In this paper, we study the device requirements of a resistive cross-point memory array under the worst-case write and read operations. We focus on the data pattern dependence of the memory array and compare the effect of the memory cell resistance values and resistance ratio for determining the maximum array size. The number of cells in the array can reach 106 with a signal swing > 50% of the reading voltage when Ron is beyond 3 M and Roff/Ron is greater than 2. A large memory cell resistance value can further reduce the power consumption, obviate the need for a large Roff/Ron ratio, and avoid the inclusion of cell selection devices. The effect of the nonlinearity of the I -V characteristics of the memory cells is also investigated. The nonlinearity calls for a substantial tradeoff between the memory cell resistance values and the resistance ratio, and must be taken into consideration for the device design. View full abstract»

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  • Electrical TCAD Simulations of a Germanium pMOSFET Technology

    Page(s): 2539 - 2546
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1119 KB) |  | HTML iconHTML  

    A commercial technology computer-aided design device simulator was extended to allow electrical simulations of sub-100-nm germanium pMOSFETs. Parameters for generation/recombination mechanisms (Shockley-Read-Hall, trap-assisted tunneling, and band-to-band tunneling) and mobility models (impurity scattering and mobility reduction at high lateral and transversal field) are provided. The simulations were found to correspond well with the experimental I- V data on our Ge transistors at gate lengths down to 70 nm and various bias conditions. The effect of changes in halo dose and extension energies is discussed, illustrating that the set of models presented in this paper can prove useful to optimize and predict the performance of new Ge-based devices. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology