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Embedded Systems Letters, IEEE

Issue 3 • Date Sept. 2010

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Displaying Results 1 - 19 of 19
  • Table of contents

    Page(s): C1
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  • IEEE Embedded Systems Letters publication information

    Page(s): C2
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  • Improving the Performance of Shared Memory Communication in Impulse C

    Page(s): 49 - 52
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (301 KB) |  | HTML iconHTML  

    With the evolution of field-programmable gate arrays (FPGAs) to the Million-Gate scope, high-level languages are gaining popularity in electronic system design, which greatly improves design and verification efficiency. Impulse C is a high-level language widely used in software/hardware (SW/HW) codesign and provides users with varies SW/HW communication mechanisms. But the communication mechanisms of Impulse C are mainly designed for versatility, and the resources within the FPGA chip is not fully utilized. In this letter, we present a improved implementation of the shared memory communication in Impulse C by utilizing both ports of the dual-port BRAM. Experiment results show that the improved implementation can greatly improve the performance of shared memory communication, and further improve the execution efficiency of hardware processes. View full abstract»

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  • Towards Fully Automatic Synthesis of Embedded Software

    Page(s): 53 - 57
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (229 KB) |  | HTML iconHTML  

    This letter presents an approach to automatically synthesize embedded software. Starting from an instruction set architecture description of a hardware platform and a formal specification of the input-output behavior of a program to be realized, a control sequence of minimal length is generated. The proposed approach uses formal techniques, i.e., the synthesis problem is mapped to an instance of satisfiability of quantified Boolean formulas. We give experimental results and discuss the advantages, as well as future challenges of the proposed approach. View full abstract»

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  • Design of a Low-Cost Underwater Acoustic Modem

    Page(s): 58 - 61
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (262 KB) |  | HTML iconHTML  

    There has been an increasing interest in creating short-range, low data rate, underwater wireless sensor networks for scientific marine exploration and monitoring. However, the lack of an inexpensive, underwater acoustic modem is preventing the proliferation of these sensor networks. Thus, we are building an underwater acoustic modem starting with the most critical component from a cost perspective-the transducer. The design substitutes a commercial transducer with a homemade transducer using cheap piezoceramic material and builds the rest of the modem's components around the properties of the transducer to extract as much performance as possible. This letter describes the high level design, and cost and power characteristics of each of the major modem components: the transducer, the analog transceiver, and the digital signal processor of our modem prototype. View full abstract»

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  • Accurate Machine-Learning-Based On-Chip Router Modeling

    Page(s): 62 - 66
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (396 KB) |  | HTML iconHTML  

    As industry moves towards multicore chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power, performance, and area has become crucially important. In this work, we develop accurate architecture-level on-chip router cost models using machine-learning-based regression techniques. Compared against existing models (e.g., ORION 2.0 and parametric models), our models reduce estimation error by up to 89% on average. View full abstract»

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  • High-Speed AES Encryptor With Efficient Merging Techniques

    Page(s): 67 - 71
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (194 KB) |  | HTML iconHTML  

    This letter presents a new efficient architecture for high-speed advanced encryption standard (AES) encryptor. This technique is implemented using composite field arithmetic byte substitution, where higher efficiency is achieved by merging and location rearrangement of different operations required in the steps of encryption. The proposed architecture is presented with multistage subpipelined architecture that allows having higher efficiency in terms of (throughput/area) than any previous field-programmable gate array (FPGA) implementations. View full abstract»

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  • A Comparative Evaluation of High-Level Hardware Synthesis Using Reed–Solomon Decoder

    Page(s): 72 - 76
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB) |  | HTML iconHTML  

    Using the example of a Reed-Solomon decoder, we provide insights into what type of hardware structures are needed to be generated to achieve specific performance targets. Due to the presence of run-time dependencies, sometimes it is not clear how the C code can be restructured so that a synthesis tool can infer the desired hardware structure. Such hardware structures are easy to express in an HDL. We present an implementation in Bluespec, a high-level HDL, and show a 7.8× improvement in performance while using only 0.45× area of a C-based implementation. View full abstract»

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  • Multi-Optical Network-on-Chip for Large Scale MPSoC

    Page(s): 77 - 80
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (667 KB) |  | HTML iconHTML  

    Optical network-on-chip (ONoC) architectures are emerging as promising contenders to solve bandwidth and latency issues in multiprocessor systems-on-chip (MPSoC). However, current on-chip integration technologies for optical interconnect allow interconnecting only dozens of IPs. Scaling with MPSoCs composed of hundreds of IPs thus, relies on unpredictable technological innovations. In this letter, we propose a method that combines multiple ONoCs. Each ONoC is small enough to rely on already existing and proven technologies. We evaluate the approach for various interconnect scenarios, showing that it scales well with the size of the MPSoC architectures. View full abstract»

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  • System-Level Energy Optimization for Error-Tolerant Image Compression

    Page(s): 81 - 84
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (554 KB) |  | HTML iconHTML  

    Based on the natural error tolerance of image and multimedia processing, aggressive voltage scaling has been considered for energy savings by trading off accuracy. However, aggressive voltage scaling in image compression may not reduce overall system energy consumption because of the reduction in the compression ratio. Based on the system-level analysis, we present an adaptive pixel and coefficient truncation technique to successfully reduce error rates so that we can achieve great energy savings without significant quality degradation. Our experimental results show that average energy savings of up to 40% can be realized at a trivial implementation cost. View full abstract»

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  • NARCO: Neighbor Aware Turn Model-Based Fault Tolerant Routing for NoCs

    Page(s): 85 - 89
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (586 KB) |  | HTML iconHTML  

    Network-on-chip (NoC) communication architectures are increasingly being used today to interconnect cores on-chip multiprocessor (CMP) based embedded systems. Permanent faults in NoCs due to fabrication challenges in sub-65 nm CMOS technologies and due to wearout underscore the need for fault tolerant design. In this letter, we propose a novel low-overhead neighbor aware, turn model based fault tolerant routing scheme (NARCO) for NoCs which combines threshold-based replication in network interfaces, a parameterizable region-based neighbor awareness in routers, and the odd-even and inverted odd-even turn models. The proposed scheme enables better packet arrival rate than state of the art, while enabling a tradeoff between communication reliability and energy overhead. View full abstract»

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  • 18th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2010)

    Page(s): 90 - 93
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  • The 10th International Conference on Formal Methods in Computer-Aided Design (FMCAD)

    Page(s): 94 - 95
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  • Embedded Systems Week

    Page(s): 96
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  • IEEE Embedded Systems Letters

    Page(s): 97
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  • Advertisement - Why we joined

    Page(s): 98
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  • Advertisement - 2011 IEEE membership form

    Page(s): 99 - 100
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  • IEEE Embedded Systems Letters Information for authors

    Page(s): C3
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  • Blank page [back cover]

    Page(s): C4
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Aims & Scope

The IEEE EMBEDDED SYSTEMS LETTERS (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software.

Full Aims & Scope

Meet Our Editors

EDITOR-IN-CHIEF
Krithi Ramamritham
Department of Computer Science and Engineering
Indian Institute of Technology Bombay

DEPUTY EDITOR-IN-CHIEF
Catherine Gebotys
Department of Electrical and Computer Engineering
University of Waterloo