Scheduled System Maintenance:
On Monday, April 27th, IEEE Xplore will undergo scheduled maintenance from 1:00 PM - 3:00 PM ET (17:00 - 19:00 UTC). No interruption in service is anticipated.
By Topic

Circuits, Devices & Systems, IET

Issue 5 • Date September 2010

Filter Results

Displaying Results 1 - 11 of 11
  • Design of non-balanced cross-coupled oscillators with no matching requirements

    Publication Year: 2010 , Page(s): 365 - 373
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (600 KB)  

    Using two-port network transmission parameters we derive the general characteristic equation of a cross-coupled circuit topology which involves two active devices and four or six impedances. The derived equations are generic and apply both to BJT or MOS transistors and even any other active device without any matching constraints. Application to realising novel non-balanced non-matched cross-coupled oscillators is demonstrated. Spice simulations of a MOS oscillator in a 0.25 technology are given as well as experimental results from an oscillator employing discrete Bipolar transistors. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-speed and low-power reconfigurable architectures of 2-digit two-dimensional logarithmic number system-based recursive multipliers

    Publication Year: 2010 , Page(s): 374 - 381
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (511 KB)  

    In new DSP applications, reconfigurable architectures have emerged to provide a flexible, high-performance, high-speed and low-power implementation platform for wireless embedded devices. Since some DSP algorithms rely heavily on multiplication, there are still demands for more efficient multiplication structures. In this study, two reconfigurable recursive multipliers are presented. The authors' architectures combine some of the flexibility of software with the high performance of hardware through implementing different levels of recursive multiplication schemes on a two-dimensional logarithmic number system (2DLNS) processing structure. The data are split into a number of smaller sections, where each section is converted to a 2-digit 2DLNS (2 bases) representation. The dynamic range reduction and logarithmic characteristics of computing with two orthogonal base exponents in this number system allows multiplication to be implemented with simple parallel small adders. The authors' architectures are able to perform single and double precision multiplications, as well as fault tolerant and dual throughput single precision operations. The implementations demonstrate the efficiency of 2DLNS in multiplication intensive DSP applications and show outstanding results in terms of operation delay and dynamic power consumption. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Concurrent error detection in semi-systolic dual basis multiplier over GF(2m) using self-checking alternating logic

    Publication Year: 2010 , Page(s): 382 - 391
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (501 KB)  

    Multiplication is one of the most important finite field arithmetic operations in cryptographic computations. Recently, the attacks of fault-based cryptanalysis have been a critical threat to both symmetrical and asymmetrical cryptosystems. To prevent such kind of attacks, masking faulty signals and outputting only correct ciphers would be a feasible solution, especially suitable for finite field multiplication. Therefore a novel dual basis multiplier in GF(2m) with concurrent error detection capability using self-checking alternating logic is presented. The new self-checking alternating logic dual basis multiplier saves about 67% space complexity as compared with other existing dual basis multiplier with concurrent error detection capability that uses the parity checking method. The proposed dual basis multiplier takes almost as low as one extra clock cycle to achieve concurrent error detection capability. Furthermore, any existing faults in fault model are ensured to be detectable through at least one input in the authors% proposed scheme. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Linear amplification by time-multiplexed spectrum

    Publication Year: 2010 , Page(s): 392 - 402
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (593 KB)  

    A new waveform processing technique for reducing intermodulation distortion (IMD) generated by an amplitude-modulated signal is presented. The technique eliminates amplifier-generated IMD by time-multiplexing portions of the signal spectrum prior to amplification. The input signal is described as a sum of sinusoidal signals. The peak-to-average ratio of the time-multiplexed amplifier input is lower than that of its non-multiplexed counterpart, but it contains spectral aliases at multiples of the switching frequency. Thus, the reduction in distortion of the desired amplified signal is achieved at the expense of momentarily widening the signal bandwidth. Following amplification, the desired signal is recovered using a bandpass filter which spreads the signal in time and narrows its bandwidth. An analytical expression for distortion reduction when amplifying two multiplexed carriers is developed along with measurements verifying the theory. Distortion reduction is demonstrated experimentally at 3.6 GHz for 2 20 multiplexed carriers, and linear recovery is demonstrated for four multiplexed carriers. The technique reduces third-order IMD by 8 22 dB in experimental measurements of three different amplifiers. The presented technique has the unique property of improving linearity without requiring feedback, feedforward cancellation or calibration. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effective design-for-testability techniques for H.264 all-binary integer motion estimation

    Publication Year: 2010 , Page(s): 403 - 413
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (878 KB)  

    H.264 is the latest video compression standard with the highest coding efficiency, and the All-Binary Integer Motion Estimation algorithm (H.264-ABIME) is usually adopted for reducing the hardware area. There are many repeated modules in the H.264-ABIME block, thus the well-known Iterative-Logic-Array (ILA) architecture can be applied to test all the modules with constant number of test patterns. The most important condition for the ILA architecture is that the I/O function of each module should be bijective (reversible). However, most of the original designs do not have this property. In this paper, effective design-for-testability schemes are proposed by using the ILA architecture for the entire H.264-ABIME block. The repeated modules are modified to be bijective and cascaded as the ILA architecture. Then each module can be fully tested by only testing the first module exhaustively. A simple built-in self-test circuit is also proposed. Moreover, the physical designs of the scan-chain and the proposed test schemes are synthesised with the UMC 0.18 m technology. The total test time of the proposed method is only about 13.53 of that of scan-chain method with automatic test pattern generation (ATPG), and the hardware and delay-time overheads are still very low. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Very large scale integration (VLSI) implementation of low-complexity variable block size motion estimation for H.264/AVC coding

    Publication Year: 2010 , Page(s): 414 - 424
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (896 KB)  

    This study presents a fast algorithm and its very large scale integration (VLSI) design to implement the variable block size motion estimation. The fast algorithm is proposed with a hardware-oriented concept for regular VLSI design. Simulations show that the proposed algorithm can reduce about 90% motion searching time, whereas PSNR only decreases about 0.02 dB on average. Based on the fast algorithm, VLSI architecture is designed with parallel structure and pipeline timing schedule to achieve high throughput rate for the HDTV system. The chip can compute 41 vectors for various block size during 24-240 cycles as using only 96 processing elements. Comparisons with contemporary VLSI architectures, this chip can offer higher processing speed, wider searching range and lower circuit complexity. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of negative differential conductance of single-island single-electron transistors owing to Coulomb oscillations

    Publication Year: 2010 , Page(s): 425 - 432
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (782 KB)  

    Despite many years of effort, the precise origin of negative differential resistance (NDR) shown by some organic layers remains unclear. Tang et al. accounted qualitatively for NDR phenomena by coulomb blockade of single-electron transistors (SETs). From this foundation, a novel method based on analysis of the charge stability diagram of a SET is proposed in this study. The method can be used to systematically analyse negative differential conductance (NDC) characteristic of a SET and some organic layers. With this method, the NDC effect is explained with respect to device parameters, and several NDC cells proposed by others are analysed in detail. The results show that this method can be efficiently used to analyse the NDC effect of SETs and some organic layers. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis and reduction of phase variations of variable gain amplifiers verified by CMOS implementation at C-band

    Publication Year: 2010 , Page(s): 433 - 439
    Cited by:  Papers (13)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (719 KB)  

    Phase variations of variable gain cascode amplifiers are analysed and a method, which significantly reduces the phase variations versus gain is presented. The operation point current and the load of the variable gain transistors are stabilised by current weighting using dummy paths. The approach is verified by a fully integrated CMOS variable gain amplifier at C-band. A maximum gain of 18 dB with a 1 dB bandwidth of 5.2 5.7 GHz is measured. At 5.7 GHz and within a gain control range of 23 dB the absolute phase difference is reduced to a minimum of ±4° yielding an improvement by a factor of 5 compared with simple cascode topologies. A total supply power of 9 mW is consumed. A very low phase variation has been achieved at comparable gain control range and power consumption for a variable gain amplifier in CMOS. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-frequency log-domain current-mode multiphase sinusoidal oscillator

    Publication Year: 2010 , Page(s): 440 - 448
    Cited by:  Papers (7)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (700 KB)  

    This study describes the design of a multiphase sinusoidal oscillator (MSO) based on log-domain filtering concept. The circuit is a direct realisation of a first-order differential equation for obtaining the inverting and non-inverting low-pass filters. Each low-pass filter comprises only a grounded capacitor and four transistors. The proposed MSO can be instantaneously controlled over a very wide frequency range by controlling the current for the oscillation frequency and oscillation condition which indicates the proposed MSO's suitability in high-frequency applications. A validated bipolar junction transistor (BJT) model is used in SPICE simulation operated from a single power supply as low as 2.5'V. The oscillation frequency is controlled over four decades of frequency. The total harmonic distortions for three phase (11.5'MHz) and four phase (7'MHz) are, respectively, obtained around 2.4 and 2.2' which enables them to be fully integrated in telecommunication systems. The power consumption is around 5.5'mW for 100''A bias current. Moreover, experimental results of three-phase MSO are included. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor– single electron transistor integrated circuits

    Publication Year: 2010 , Page(s): 449 - 457
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1091 KB)  

    For the first time, the impact of energy quantisation in single electron transistor (SET) island on the performance of hybrid complementary metal oxide semiconductor (CMOS)-SET transistor circuits has been studied. It has been shown through simple analytical models that energy quantisation primarily increases the Coulomb Blockade area and Coulomb Blockade oscillation periodicity of the SET device and thus influences the performance of hybrid CMOS-SET circuits. A novel computer aided design (CAD) framework has been developed for hybrid CMOS-SET co-simulation, which uses Monte Carlo (MC) simulator for SET devices along with conventional SPICE for metal oxide semiconductor devices. Using this co-simulation framework, the effects of energy quantisation have been studied for some hybrid circuits, namely, SETMOS, multiband voltage filter and multiple valued logic circuits. Although energy quantisation immensely deteriorates the performance of the hybrid circuits, it has been shown that the performance degradation because of energy quantisation can be compensated by properly tuning the bias current of the current-biased SET devices within the hybrid CMOS-SET circuits. Although this study is primarily done by exhaustive MC simulation, effort has also been put to develop first-order compact model for SET that includes energy quantisation effects. Finally, it has been demonstrated that one can predict the SET behaviour under energy quantisation with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Frequency compensation for two-stage operational amplifiers with improved power supply rejection ratio characteristic

    Publication Year: 2010 , Page(s): 458 - 467
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (571 KB)  

    A frequency compensation technique improving characteristic of power supply rejection ratio (PSRR) for two-stage operational amplifiers is presented. This technique is applicable to most known two-stage amplifier configurations. The detailed small-signal analysis of an exemplary amplifier with the proposed compensation and a comparison to its basic version reveal several benefits of the technique which can be effectively exploited in continuous-time filter designs. This comparison shows the possibility of PSRR bandwidth broadening of more than a decade, significant reduction of chip area, the unity-gain bandwidth and power consumption improvement. These benefits are gained at the cost of a non-monotonic phase characteristic of the open-loop differential voltage gain and limitation of a close-loop voltage gain. A prototype-integrated circuit, fabricated based on 0.35 μm complementary metal-oxide semiconductor technology, was used for the technique verification. Two pairs of amplifiers with the classical Miller compensation and a cascoded input stage were measured and compared to their improved counterparts. The measurement data fully confirm the theoretically predicted advantages of the proposed compensation technique. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

IET Circuits, Devices & Systems covers the following topics:

Circuit theory and design, circuit analysis and simulation, computer aided design; filters (analogue and switched capacitor); circuit implementations, cells and architectures for integration including VLSI; testability, fault tolerant design, minimisation of circuits and CAD for VLSI; novel or improved electronic devices for both traditional and emerging technologies including nanoelectronics and MEMs, device and process characterisation, device parameter extraction schemes; mathematics of circuits and systems theory; test and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers.

Full Aims & Scope

Meet Our Editors

Publisher
IET Research Journals
iet_cds@theiet.org