# IEEE Transactions on Computers

## Filter Results

Displaying Results 1 - 15 of 15
• ### [Front cover]

Publication Year: 2010, Page(s): c1
| PDF (103 KB)
• ### [Inside front cover]

Publication Year: 2010, Page(s): c2
| PDF (105 KB)
• ### Low Complexity Cubing and Cube Root Computation over $F_{3^m}$ in Polynomial Basis

Publication Year: 2010, Page(s):1297 - 1308
Cited by:  Papers (8)
| | PDF (2929 KB) | HTML

We present low complexity formulae for the computation of cubing and cube root over IF3m constructed using special classes of irreducible trinomials, tetranomials and pentanomials. We show that for all those special classes of polynomials, field cubing and field cube root operation have the same computational complexity when implemented in hardware or software platforms. As o... View full abstract»

• ### A low hardware overhead self-diagnosis technique using reed-solomon codes for self-repairing chips

Publication Year: 2010, Page(s):1309 - 1319
Cited by:  Papers (5)
| | PDF (2544 KB) | HTML

A self-diagnosis circuit that can be used for built-in self-repair is proposed. The circuit under diagnosis is assumed to be composed of a large number of field repairable units (FRUs), which can be replaced with spares when they are found to be defective. Since the proposed self-diagnosis circuit is implemented on the chip, responses that are scanned out of scan chains are compressed by the group... View full abstract»

• ### Stability-Optimized Time Adjustment for a Networked Computer Clock

Publication Year: 2010, Page(s):1320 - 1336
| | PDF (2276 KB) | HTML

We propose an optimal time adjustment method from the viewpoint of frequency stability, which is defined as the Allan deviation. When time adjustment is needed for a clock in a networked computer, it is made over a period called a time adjustment period. The proposed method optimizes frequency stability for a given time adjustment period. This method has been evaluated and compared with the adjtim... View full abstract»

• ### A Hybrid Approach to NAND-Flash-Based Solid-State Disks

Publication Year: 2010, Page(s):1337 - 1349
Cited by:  Papers (32)  |  Patents (1)
| | PDF (2063 KB) | HTML

Replacing power-hungry disks with NAND-flash-based solid-state disks (SSDs) is a recently emerging trend in flash-memory applications. One important SSD design issue is achieving a good balance between cost, performance, and lifetime. This study introduces a hybrid approach to large SSDs that combines MLC NAND flash and SLC NAND flash. Each of these flash architectures has its own drawbacks and be... View full abstract»

• ### DACO: A High-Performance Disk Architecture Designed Specially for Large-Scale Erasure-Coded Storage Systems

Publication Year: 2010, Page(s):1350 - 1362
Cited by:  Papers (5)
| | PDF (2651 KB) | HTML

Large-scale erasure-coded storage systems have a serious performance problem due to I/O congestion and disk media access congestion caused by read-modify-write operations involved in small-write operations. All the existing technologies based on the conventional disk can provide very limited performance improvement. This paper presents a new Disk Architecture with Composite Operation (DACO), whose... View full abstract»

• ### Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization

Publication Year: 2010, Page(s):1363 - 1377
Cited by:  Papers (13)
| | PDF (3237 KB) | HTML

We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator (HA), the latter having full master-mode access to memory. We then describe how the resulting requirements can actually be realized efficiently in a custom computer by hardware architecture and system software measures. ... View full abstract»

• ### Packet-Mode Emulation of Output-Queued Switches

Publication Year: 2010, Page(s):1378 - 1391
Cited by:  Papers (5)
| | PDF (1034 KB) | HTML

Most common network protocols transmit variable size packets, whereas contemporary switches still operate with fixed- size cells, which are easier to transmit and buffer. This necessitates packet segmentation and reassembly modules, resulting in significant computation and communication overhead that might be too costly as switches become faster and bigger. It is, therefore, imperative to investig... View full abstract»

• ### On the Security of Public-Key Algorithms Based on Chebyshev Polynomials over the Finite Field $Z_N$

Publication Year: 2010, Page(s):1392 - 1401
Cited by:  Papers (11)
| | PDF (1220 KB) | HTML

In this paper, the period distribution of sequences generated by Chebyshev polynomials over the finite field ZN is analyzed. It is found that the distribution is unsatisfactory if N (the modulus) is not chosen properly. Based on this finding, we present an attack on the public-key algorithm based on Chebyshev polynomials over ZN. Then, we modify the original algorithm to make... View full abstract»

• ### Stochastic Contention Level Simulation for Single-Chip Heterogeneous Multiprocessors

Publication Year: 2010, Page(s):1402 - 1418
Cited by:  Papers (2)
| | PDF (2879 KB) | HTML

Single-chip systems, featuring multiple heterogeneous processors and a variety of communication and memory architectures, have emerged to satisfy the demand for networking, handheld computing, and other custom devices. When simulated at cycle-accurate level, these system models are slow to build and execute, severely limiting the number of design iterations that can be considered. A key challenge ... View full abstract»

• ### Performability Analysis of Multistate Computing Systems Using Multivalued Decision Diagrams

Publication Year: 2010, Page(s):1419 - 1433
Cited by:  Papers (10)
| | PDF (5097 KB) | HTML

A distinct characteristic of multistate systems (MSS) is that the systems and/or their components may exhibit multiple performance levels (or states) varying from perfect operation to complete failure. MSS can model behaviors such as shared loads, performance degradation, imperfect fault coverage, standby redundancy, limited repair resources, and limited link capacities. The nonbinary state proper... View full abstract»

• ### Load Unbalancing Strategy for Multicore Embedded Processors

Publication Year: 2010, Page(s):1434 - 1440
Cited by:  Papers (10)
| | PDF (1432 KB) | HTML

Load balancing has been known as an essential feature for enhancing the performance of distributed systems. For embedded systems, however, this is not always true since load balancing leads to lavish power consumption by fully utilizing all the embedded cores even for a small number of tasks. Furthermore, the previously proposed load unbalancing strategies do not concern much about the characteris... View full abstract»

• ### TC Information for authors

Publication Year: 2010, Page(s): c3
| PDF (105 KB)
• ### [Back cover]

Publication Year: 2010, Page(s): c4
| PDF (103 KB)

## Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24
10129 Torino - Italy
e-mail: pmo@computer.org