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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 9 • Date Sept. 2010

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Displaying Results 1 - 18 of 18
  • Table of contents

    Publication Year: 2010 , Page(s): C1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2010 , Page(s): C2
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  • Designing Heterogeneous Embedded Network-on-Chip Platforms With Users in Mind

    Publication Year: 2010 , Page(s): 1301 - 1314
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2340 KB) |  | HTML iconHTML  

    In this paper, we propose a user-centric design methodology targeting heterogeneous embedded systems-on-chip where communication happens via the network-on-chip approach. More precisely, in this new design methodology, we consider explicitly the information about the user experience and apply machine learning techniques to develop a design flow which aims at minimizing the workload variance; this ... View full abstract»

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  • ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochips

    Publication Year: 2010 , Page(s): 1315 - 1327
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (986 KB) |  | HTML iconHTML  

    Digital microfluidic biochips have emerged as a popular alternative for laboratory experiments. To make the biochip feasible for practical applications, pin-count reduction is a key problem to higher-level integration of reactions on a biochip. Most previous works approach the problem by post-processing the placement and routing solutions to share compatible control signals; however, the quality o... View full abstract»

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  • Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation

    Publication Year: 2010 , Page(s): 1328 - 1341
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (715 KB) |  | HTML iconHTML  

    Considerable effort has been expended in the electronic design automation community in trying to cope with the statistical timing problem. Most of this effort has been aimed at generalizing the static timing analyzers to the statistical case. On the other hand, detailed transistor-level simulations of the critical paths in a circuit are usually performed at the final stage of performance verificat... View full abstract»

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  • Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling

    Publication Year: 2010 , Page(s): 1342 - 1353
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1601 KB) |  | HTML iconHTML  

    Clock meshes possess inherent low clock skews and excellent immunity to process-voltage-temperature variations, and have increasingly found their way to high-performance integrated circuit designs. However, analysis of such massively coupled networks is significantly hindered by the sheer size of the network and tight coupling between non-tree interconnects and large numbers of clock drivers. Whil... View full abstract»

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  • PABTEC: Passivity-Preserving Balanced Truncation for Electrical Circuits

    Publication Year: 2010 , Page(s): 1354 - 1367
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (914 KB) |  | HTML iconHTML  

    We present a passivity-preserving balanced truncation model reduction method for differential-algebraic equations arising in circuit simulation. This method is based on balancing the solutions of projected Lur'e equations. By making use of the special structure of circuit equations, we can reduce the numerical effort for balanced truncation significantly. It is shown that the property of reciproci... View full abstract»

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  • On the Scalability and Dynamic Load-Balancing of Optimistic Gate Level Simulation

    Publication Year: 2010 , Page(s): 1368 - 1380
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1165 KB) |  | HTML iconHTML  

    As proscribed by Moore's law, the size of integrated circuits has grown geometrically, resulting in simulation becoming the major bottleneck in the circuit design process. Parallel simulation provides us with a way to cope with this growth. In this paper, we describe an optimistic (time warp) parallel discrete event simulator which can simulate all synthesizeable Verilog circuits. We investigate i... View full abstract»

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  • Temperature-Aware Integrated DVFS and Power Gating for Executing Tasks With Runtime Distribution

    Publication Year: 2010 , Page(s): 1381 - 1394
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1970 KB) |  | HTML iconHTML  

    At high-operating temperature, chip cooling is crucial due to the exponential temperature dependence of leakage current. However, traditional cooling methods, e.g., power/clock gating applied when a temperature threshold is reached, often cause excessive performance degradation. In this paper, we propose a method for delivering lower energy consumption by integrating the cooling and running in a t... View full abstract»

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  • Supervised Learning Based Power Management for Multicore Processors

    Publication Year: 2010 , Page(s): 1395 - 1408
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1333 KB) |  | HTML iconHTML  

    This paper presents a supervised learning based power management framework for a multi-processor system, where a power manager (PM) learns to predict the system performance state from some readily available input features (such as the occupancy state of a global service queue) and then uses this predicted state to look up the optimal power management action (e.g., voltage-frequency setting) from a... View full abstract»

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  • Gate-Sizing-Based Single V_{\rm dd} Test for Bridge Defects in Multivoltage Designs

    Publication Year: 2010 , Page(s): 1409 - 1421
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1507 KB) |  | HTML iconHTML  

    The use of multiple voltage settings for dynamic power management is an effective design technique. Recent research has shown that testing for resistive bridging faults in such designs requires more than one voltage setting for 100% fault coverage; however, switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes an effective gate ... View full abstract»

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  • Modular Datapath Optimization and Verification Based on Modular-HED

    Publication Year: 2010 , Page(s): 1422 - 1435
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1387 KB) |  | HTML iconHTML  

    This paper proposes an automatic design flow of datapath-dominated applications which is able to deal with optimization and equivalence checking of multi-output polynomials over Z2n. This paper also gives four main contributions: 1) proposing a complete design flow for modular equivalence checking, high level synthesis, and optimization; 2) considering hidden monomials to fac... View full abstract»

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  • Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers

    Publication Year: 2010 , Page(s): 1436 - 1448
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (866 KB) |  | HTML iconHTML  

    Modern assertion languages such as property specification language (PSL) and SystemVerilog assertions include many language constructs. By far, the most economical way to process the full languages in automated tools is to rewrite the majority of operators to a small set of base cases, which are then processed in an efficient way. Since recent rewrite attempts in the literature have shown that the... View full abstract»

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  • Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage

    Publication Year: 2010 , Page(s): 1449 - 1453
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (266 KB) |  | HTML iconHTML  

    Transition path delay faults were defined to capture the behavior of both small and large delay defects in a single fault model. The number of detectable transition path delay faults as defined earlier is the same or close to the number of conventional path delay faults that are detectable under the strong non-robust propagation conditions. When the weak non-robust propagation conditions are used,... View full abstract»

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  • IEEE copyright form

    Publication Year: 2010 , Page(s): 1454 - 1455
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2010 , Page(s): 1456
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2010 , Page(s): C3
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  • Blank page [back cover]

    Publication Year: 2010 , Page(s): C4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu