IEEE Transactions on Electron Devices

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Publication Year: 2010, Page(s):C1 - 1726
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• IEEE Transactions on Electron Devices publication information

Publication Year: 2010, Page(s): C2
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• Changes in the Editorial Board

Publication Year: 2010, Page(s): 1727
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• A Novel Self-Aligned 4-Bit SONOS-Type Nonvolatile Memory Cell With T-Gate and I-Shaped FinFET Structure

Publication Year: 2010, Page(s):1728 - 1736
Cited by:  Papers (3)
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We propose a novel 4-bit self-aligned SONOS-type nonvolatile memory (NVM) cell with a T-gate and I-shaped FinFET structure for practical implementation with high storage density and better reliability. In order to obtain enhanced reliability characteristics, a modified Fowler-Nordheim tunneling mechanism is employed for programming along the channel length direction, while a band-to-band hot hole ... View full abstract»

• P-Channel Nonvolatile Flash Memory With a Dopant-Segregated Schottky-Barrier Source/Drain

Publication Year: 2010, Page(s):1737 - 1742
Cited by:  Papers (4)
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A p-channel dopant-segregated-Schottky-barrier (DSSB) device based on a SOI FinFET structure is proposed for silicon-oxide-nitride-oxide-silicon type Flash memory, providing the feasibility of bit-by-bit operation through the aid of a symmetric program/erase operation. This concept is based on utilizing injected holes due to enhanced Fowler-Nordheim tunneling probability triggered by the sharpened... View full abstract»

• Bipolar Mode Operation and Scalability of Double-Gate Capacitorless 1T-DRAM Cells

Publication Year: 2010, Page(s):1743 - 1750
Cited by:  Papers (15)  |  Patents (28)
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In this paper, we study the operation mode and the scalability of the second generation (type II) of double-gate capacitorless one transistor dynamic random access memory (1T-DRAM) cells. We find that the memory operates by accumulating charge at the gate interfaces, not in the body of the cell. The type-II configuration allows an infinitely long retention of state “1,” whereas the t... View full abstract»

• A Unified Method for Calculating Capacitive and Resistive Coupling Exploiting Geometry Constraints on Lightly and Heavily Doped CMOS Processes

Publication Year: 2010, Page(s):1751 - 1760
Cited by:  Papers (8)
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A method for calculating capacitive and resistive coupling is developed in this work, and its implementation in commonly encountered practical cases is presented. The method is based on the geometry of the coupling mechanism, and the derived model is therefore, in general, scalable and technology independent. The constraints of any related problem can easily be incorporated into this method, where... View full abstract»

• Fundamental Limitations to the Width of the Programmed $V_{T}$ Distribution of nor Flash Memories

Publication Year: 2010, Page(s):1761 - 1767
Cited by:  Papers (7)
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This paper presents experimental evidences of the granular electron injection during channel hot-electron programming of NOR Flash memories. The statistical process ruling the discrete charge transfer from the substrate to the floating gate is shown to introduce a fundamental spread contribution to the programmed threshold-voltage distribution obtained by the staircase algorithm, determining its u... View full abstract»

• A Compact Space and Efficient Drain Current Design for Multipillar Vertical MOSFETs

Publication Year: 2010, Page(s):1768 - 1773
Cited by:  Papers (4)  |  Patents (4)
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In the vertical MOSFET, due to its device structure, the bottom of its silicon pillar has a certain resistance because there is a diffused silicon wiring area in the bottom. Thereby, this resistance becomes large in the case of the multipillar transistors and also shows asymmetric characteristics between the top and bottom nodes of the pillar. This paper is devoted to examining this resistance for... View full abstract»

• Nonvolatile Schottky Barrier Multibit Cell With Source-Side Injected Programming and Reverse Drain-Side Hole Erasing

Publication Year: 2010, Page(s):1774 - 1780
Cited by:  Papers (15)
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This paper presents a novel Schottky barrier multibit cell with source-side injected programming and reverse drain-side hole erasing. Based on the unique ambipolar conduction of Schottky barrier devices, the source Schottky barrier promotes the amounts of hot electrons at a positive gate voltage to perform source-side injected programming, whereas the drain Schottky barrier enhances the generation... View full abstract»

• Reduction of Bipolar Disturb of Floating-Body Cell (FBC) by Silicide and Thin Silicon Film Formed at Source and Drain Regions

Publication Year: 2010, Page(s):1781 - 1788
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The cell-to-cell leakage caused by bipolar disturb of the floating-body cell (FBC) has been investigated. In the case of FBC without silicide at the source and drain regions, the change of data “0” to data “1” has been observed in the writing operation to the adjacent cell. However, this leakage can be reduced when the silicide is formed on the thin silicon film at the ... View full abstract»

• Thermal Design of Multifinger Bipolar Transistors

Publication Year: 2010, Page(s):1789 - 1800
Cited by:  Papers (4)
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In this paper, design guidelines are provided to improve the thermal stability of three- and four-finger bipolar transistors. Experiments and simulations are first performed on silicon-on-glass (SOG) three-finger bipolar junction transistors (BJTs) with self-heating and mutual thermal resistances varying in a large range of values, depending on the silicon area, presence of heat spreaders, isolati... View full abstract»

• Effects of Vanadium Doping on Resistive Switching Characteristics and Mechanisms of $hbox{SrZrO}_{3}$-Based Memory Films

Publication Year: 2010, Page(s):1801 - 1808
Cited by:  Papers (31)  |  Patents (1)
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The effects of vanadium doping on resistive switching (RS) characteristics and mechanisms of RF-sputtered SrZrO3 (SZO)-based thin films are investigated in this paper. The physical and electrical properties of SZO-based thin films are modulated by vanadium doping due to the Zr4+ ion replaced by V5+, further affecting the RS parameters of SZO-based thin films. The c... View full abstract»

• Measurement of Dipoles/Roll-Off /Work Functions by Coupling CV and IPE and Study of Their Dependence on Fabrication Process

Publication Year: 2010, Page(s):1809 - 1819
Cited by:  Papers (15)
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We study the effective metal gate work function (WFMeff) of different metal/high-κ gate stacks. Both capacitance versus voltage measurement and internal photo emission measurement were used, leading to a better understanding of the WFMeff variations. We demonstrate that these variations are related to two main process dependent parameters, a voltage drop at the high- &... View full abstract»

• Analytical Approximation for the Surface Potential in n-Channel MOSFETs Considering Quantum–Mechanical Effects

Publication Year: 2010, Page(s):1820 - 1828
Cited by:  Papers (10)
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A physics-based analytical model for the surface potential in n-channel MOSFETs considering quantum-mechanical effects in the inversion region is presented. The model is continuous from the accumulation to strong inversion regions of operation. The results from the model show excellent agreement with the values obtained from a self-consistent solution of the Schrödinger and Poisson equatio... View full abstract»

• Performance and Reliability Study of Single-Layer and Dual-Layer Platinum Nanocrystal Flash Memory Devices Under NAND Operation

Publication Year: 2010, Page(s):1829 - 1837
Cited by:  Papers (7)
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Memory window (MW) and the retention of single-layer (SL) and dual-layer (DL) platinum (Pt) nanocrystal (NC) devices are extensively studied before and after program/erase (P/E) cycling. DL devices show better charge storage capability and reliability over the SL devices. Up to 50% improvement in the stored charge is estimated in the DL device over SL when P/E is performed at equal field. Excellen... View full abstract»

• A New Transient Model for Recovery and Relaxation Oscillations in Phase-Change Memories

Publication Year: 2010, Page(s):1838 - 1845
Cited by:  Papers (12)
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Phase-change memory (PCM) relies not only on phase transitions between the two structures of the chalcogenide materials but also on electronic switching in the amorphous material between off and on conductive states and vice versa. Transient effects associated to both transitions, like the delay time for threshold switching, the switching time, and the recovery time for the on to off transi... View full abstract»

• Analytical Model of Short-Channel Double-Gate JFETs

Publication Year: 2010, Page(s):1846 - 1855
Cited by:  Papers (16)
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In this paper, we propose a compact model of the short-channel double-gate (DG) JFETs, which are devices intended for low-power logic applications. In order to make the current equation continuous through all operating conditions from the subthreshold to well above the threshold without nonphysical fitting parameters, mobile carriers in depletion regions are considered. For describing the short-ch... View full abstract»

• Harvesting and Transferring Vertical Pillar Arrays of Single-Crystal Semiconductor Devices to Arbitrary Substrates

Publication Year: 2010, Page(s):1856 - 1864
Cited by:  Papers (26)
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Development of devices that can be fabricated on amorphous substrates using multiple single-crystal semiconductors with different physical, electrical, and optical characteristics is important for highly efficient portable and flexible electronics, optoelectronics, and energy conversion devices. Reducing the use of single-crystal substrates can contribute to low-cost and environmentally benign dev... View full abstract»

• Investigation of Moisture Uptake in Low-$kappa$ Dielectric Materials

Publication Year: 2010, Page(s):1865 - 1872
Cited by:  Papers (9)
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The influence of moisture on the electrical properties of PECVD SiCOH and a PECVD porous ultralow- κ (pULK) material has been investigated in comparison with a thermal oxide and a PECVD oxide. Capacitance-time (C -t) measurements are performed on metal-insulator-metal structures during exposure to different humidity conditions (0% to 80% RH) to determine the effect on the rela... View full abstract»

• Transient Device Simulation of Floating Gate Nonvolatile Memory Cell With a Local Trap

Publication Year: 2010, Page(s):1873 - 1882
Cited by:  Papers (4)
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The single-electron general-purpose device simulator is improved to carry out a wide-range transient analysis from 1 ps to 10 years. We apply this simulator to a floating gate (FG) nonvolatile memory cell in order to simulate a degradation mode of data retention owing to the direct tunneling enhanced by the fixed charge stored by a local trap in an interpoly dielectric. The scaling impact of ideal... View full abstract»

• $hbox{Ge-Si}_{x}hbox{Ge}_{1 - x}$ Core–Shell Nanowire Tunneling Field-Effect Transistors

Publication Year: 2010, Page(s):1883 - 1888
Cited by:  Papers (17)
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We report the fabrication and experimental investigation of Ge-SixGe1-xcore-shell nanowire (NW) tunneling field-effect transistors (TFETs), consisting of p-i-n device structures realized by low-energy ion implantation. We investigate the NW TFET device characteristics as a function of drain doping, channel length, and temperature. Our devices show on-state currents of up t... View full abstract»

• External Stresses on Tensile and Compressive Contact Etching Stop Layer SOI MOSFETs

Publication Year: 2010, Page(s):1889 - 1894
Cited by:  Papers (7)
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A n-/p-SOI MOSFET capped with a standard 380 Å tensile contact etching stop layer (CESL) and a 700 Å compressive CESL and with SOI thicknesses of 500/700/900 Å were measured in this paper. Additionally, external uniaxial compressive stresses with both longitudinal and transverse directions up to 45.7 MPa were applied on the devices sitting on cut silicon bars. Temperature-indu... View full abstract»

• Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals

Publication Year: 2010, Page(s):1895 - 1902
Cited by:  Papers (6)
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In this paper, silicon-oxide-nitride-oxide-semiconductor (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method with multilevel and 2-b/cell operation have been successfully demonstrated. The proposed in situ Si-NC deposition method exhibits the advantages of low cost, simplicity, and compatibility with modern IC processes. SONOS memories with embedded ... View full abstract»

• Sb-HEMT: Toward 100-mV Cryogenic Electronics

Publication Year: 2010, Page(s):1903 - 1909
Cited by:  Papers (15)
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In this paper, we present a first full set of characteristics (dc, fT, fmax, and noise) of InAs/AlSb high-electron mobility transistors (HEMTs) operating under cryogenic temperature and low-power conditions. Those results are systematically compared and deeply analyzed at room temperature and 77 K. The characteristics improvement achieved at 77 K open up the possibility to de... View full abstract»

Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy