# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 21 of 21

Publication Year: 2010, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2010, Page(s): C2
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• ### A High-Performance Unified-Field Reconfigurable Cryptographic Processor

Publication Year: 2010, Page(s):1145 - 1158
Cited by:  Papers (17)
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With rapid increases in communication and network applications, cryptography has become a crucial issue to ensure the security of transmitted data. In this paper, we propose a microcode-based architecture with a novel reconfigurable datapath which can perform either prime field GF(p) operations or binary extension field GF(2m) operations for arbitrary prime numbers, irreducible p... View full abstract»

• ### Time-Multiplexed Compressed Test of SOC Designs

Publication Year: 2010, Page(s):1159 - 1172
Cited by:  Papers (6)  |  Patents (1)
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In this paper we observe that the necessary amount of compressed test data transferred from the tester to the embedded cores in a system-on-a-chip (SOC) varies significantly during the testing process. This motivates a novel approach to compressed system-on-a-chip testing based on time-multiplexing the tester channels. It is shown how the introduction of a few control channels will enable the shar... View full abstract»

• ### Variation-Aware System-Level Power Analysis

Publication Year: 2010, Page(s):1173 - 1184
Cited by:  Papers (3)  |  Patents (1)
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The operational characteristics of integrated circuits in nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufacturing process and the operating environment. In this paper, we address the problem of incorporating the effects of variations into system-level power analysis tools. We consider both manufacturing-induced (die-to-die and within-die) vari... View full abstract»

• ### An Energy Efficient Layered Decoding Architecture for LDPC Decoder

Publication Year: 2010, Page(s):1185 - 1195
Cited by:  Papers (11)  |  Patents (2)
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Low-density parity-check (LDPC) decoder requires large amount of memory access which leads to high energy consumption. To reduce the energy consumption of the LDPC decoder, memory-bypassing scheme has been proposed for the layered decoding architecture which reduces the amount of access to the memory storing the soft posterior reliability values. In this work, we present a scheme that achieves the... View full abstract»

• ### C-Pack: A High-Performance Microprocessor Cache Compression Algorithm

Publication Year: 2010, Page(s):1196 - 1208
Cited by:  Papers (30)  |  Patents (1)
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Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memory. Accessing off-chip memory generally takes an order of magnitude more time than accessing on-chip cache, and two orders of magnitude more time than executing an instruction. Computer systems and microarchitecture resea... View full abstract»

• ### A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors

Publication Year: 2010, Page(s):1209 - 1219
Cited by:  Papers (7)
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Due to their small sizes, SRAMs are particularly vulnerable to parametric failures, resulting in significantly reduced yield. The underlying problem with SRAM is that there are conflicting requirements for read stability and writeability, such that optimizing the cell for read stability degrades its writeability. In this work, we present a circuit-architecture co-design technique that allows the d... View full abstract»

• ### On Reducing Test Power and Test Volume by Selective Pattern Compression Schemes

Publication Year: 2010, Page(s):1220 - 1224
Cited by:  Papers (5)
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In modern chip designs, test strategies are becoming one of the most important issues due to the increase of the test cost, among them we focus on the large test power dissipation and large test data volume. In this paper, we develop a methodology to suppress the test power to avoid chip failures caused by large test power, and our methodology is also effective in reducing the test data volume and... View full abstract»

• ### Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing

Publication Year: 2010, Page(s):1225 - 1229
Cited by:  Papers (57)  |  Patents (1)
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In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to it... View full abstract»

• ### Robust Fault Models Where Undetectable Faults Imply Logic Redundancy

Publication Year: 2010, Page(s):1230 - 1234
Cited by:  Papers (3)
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We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy. The stuck-at fault model is robust, but other fault models such as certain bridging and interconnect open fault models are not. A robust fault model provides a mechanism to synthesize circuits in which all the target faults are detectable and 100% fault coverage is achi... View full abstract»

• ### Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over ${rm GF}(2^{m})$ Using Multiple Parity Prediction Schemes

Publication Year: 2010, Page(s):1234 - 1238
Cited by:  Papers (8)
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New bit-serial architectures with concurrent error detection capability are presented to detect erroneous outputs in bit-serial normal basis multipliers over GF(2m) using single and multiple-parity prediction schemes. It is shown that different types of normal basis multipliers could be realized by similar architectures. The proposed architectures can detect errors with nearly 100% prob... View full abstract»

• ### Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration

Publication Year: 2010, Page(s):1238 - 1243
Cited by:  Papers (6)
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Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additiona... View full abstract»

• ### On the Power Management of Simultaneous Multithreading Processors

Publication Year: 2010, Page(s):1243 - 1248
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Simultaneous multithreading (SMT) processors are widely used in high performance computing tasks. However, with the improved performance of the SMT architecture, the utilization of their functional units is significantly increased, straining the power budget of the processor. This increases not only the dynamic power consumption, but also the leakage power consumption due to the increased temperat... View full abstract»

• ### Register File Partitioning and Compiler Support for Reducing Embedded Processor Power Consumption

Publication Year: 2010, Page(s):1248 - 1252
Cited by:  Papers (6)
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Register file (RF) in modern embedded processors contributes a substantial budget in the energy consumption due to its large switching capacitance and long working time. For embedded processors, on average 25% of registers count for 83% of RF accessing time. This motivates us to partition the RF into hot and cold regions, with the most frequently used registers placed in the hot region, and the ra... View full abstract»

• ### An Adaptive Algorithm for Single-Electron Device and Circuit Simulation

Publication Year: 2010, Page(s):1253 - 1257
Cited by:  Papers (2)
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Single-electron devices have been widely used in electronics and physics research, and are believed to be one of the potential alternatives to CMOS circuits due to their small size and ultra-low power dissipation. In the recent past, three simulation methods have been used for single-electron device and circuit analysis: the Monte Carlo method, the master equation method, and SPICE using analytic ... View full abstract»

• ### Low-Cost and Energy-Efficient Distributed Synchronization for Embedded Multiprocessors

Publication Year: 2010, Page(s):1257 - 1261
Cited by:  Papers (3)
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We present a framework for a distributed and lowcost implementation of synchronization mechanisms for embedded shared-memory multiprocessors. The proposed architecture effectively implements the queued-lock semantics in a completely decentralized manner through low-cost and distributed synchronization controllers performing distributed synchronization management protocols. The proposed approach ac... View full abstract»

• ### Corrections to “Unified Logical Effort—A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect” [May 10 689-696]

Publication Year: 2010, Page(s): 1262
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In the above titled paper (ibid., vol. 18, no. 5, pp. 689-696, May 10), the formula and the caption in Fig. 3 appeared incorrectly. The correct figure is presented here along with an explanation. View full abstract»

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Publication Year: 2010, Page(s): 1263
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

Publication Year: 2010, Page(s): 1264
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

Publication Year: 2010, Page(s): C3
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## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu