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Computers & Digital Techniques, IET

Issue 4 • Date July 2010

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Displaying Results 1 - 8 of 8
  • A Galois field-based logic synthesis with testability

    Page(s): 263 - 273
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (568 KB)  

    In deep-submicron very-large-scale integration (VLSI) systems, efficient circuit testability is one of the most demanding requirements. An automatic synthesis technique for designing efficiently testable logic circuits is one of the ways to tackle the problem. To this end, this study introduces the generalised theory and a new fast efficient graph-based decomposition technique for the functions over finite fields defined over the set GF(N), where N is a power of a prime number, which utilises the data structure of the multiple-output decision diagrams. In particular, the proposed technique can decompose any N valued arbitrary function over the fields conjunctively and disjunctively. The proposed technique is capable of generating testable circuits. The experimental results show that the proposed method is more economical in terms of literal count compared to the existing approaches. Furthermore, the authors have shown that the basic block can be tested with only eight test vectors. View full abstract»

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  • Test pattern generation for droop faults

    Page(s): 274 - 284
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (569 KB)  

    In nanometer ICs, when several transistors in physical proximity switch within the same clock cycle, a substantial power supply drop, known as droop, may occur because of concurrent load on a via of the power grid. Transistors may slow down because of lower supply voltage. Modelling of such timing faults, termed as droop faults, and their impact on the functionality and timing behaviour of the circuit are yet to be fully understood. In this study, a simple automatic test pattern generation (ATPG) based procedure for stuck-at faults has been adapted to test droop faults. For validation of the methodology in combinational circuits and full scan sequential circuits, a set of appropriate clusters of gates is selected to cover potential droop-prone regions in a circuit. Experimental results on ISCAS-85 and ISCAS-89 benchmark circuits reveal that a very high droop fault coverage can be obtained by applying a short sequence of test vectors. View full abstract»

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  • Low power design of phase-change memory based on a comprehensive model

    Page(s): 285 - 292
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (658 KB)  

    In this study, the authors propose non-conventional phase-change memory programming schemes using a comprehensive model, which integrates the underlying electrical and thermal theories. Various pulsing schemes aiming to reduce operation power without compromising performance are assessed based on a calibrated model. Our results suggest that optimisation of power consumption can be done simply by design of pulsing techniques. View full abstract»

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  • Energy-aware instruction cache design using small trace cache

    Page(s): 293 - 305
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (626 KB)  

    An instruction cache consumes a significant amount of energy in modern microprocessors. Therefore energy efficiency as well as performance should be considered when designing instruction cache architecture, especially for embedded processors. The authors propose a new instruction cache architecture for reducing dynamic energy consumption with negligible performance degradation, unlike typical architecture-level approaches which reduce dynamic energy consumption by sacrificing performance. The proposed instruction cache is composed of two caches: a large main instruction cache and a small low-power trace cache (LPT-cache). When a request comes into the proposed cache, either main instruction cache or LPT-cache is only accessed by utilising the information from the modified branch target buffer which enables predictions with very high accuracy. The proposed technique reduces the dynamic energy consumption significantly by replacing the accesses to a large main instruction cache with those to a small LPT-cache. Simulation results show that the proposed technique reduces dynamic energy consumption by 14.6% on average with negligible performance degradation over the traditional instruction cache. View full abstract»

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  • Field programmable gate array prototyping of end-around carry parallel prefix tree architectures

    Page(s): 306 - 316
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (375 KB)  

    As an important part of many processors's floating point unit, fused multiply-add unit performs a multiplication followed immediately by an addition. In IBM POWER6 microprocessor's fused multiply-add unit, a fast 128-bit floating-point end-around-carry (EAC) adder is proposed. Very few algorithmic details exist in today's literature about this adder. In this study, a complete designed EAC adder that can work independently as a regular adder is proposed. Details about the proposed EAC adder's arithmetic algorithms are described. In IBM's original EAC adder, the Kogge'Stone tree has been chosen for its high performance on ASIC technology. In this study, the authors present a comparative study on different parallel prefix trees which are used in the design of our new EAC adder targeting field programmable gate array (FPGA) technology. Our study highlights the main performance differences among 14 different architecture configurations focusing on the area requirements and the critical path delay. The experimental results show that there is one architecture configuration with the lower area requirement and the higher performance. View full abstract»

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  • Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction

    Page(s): 317 - 324
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (343 KB)  

    Large test data volume and excessive test power are two strict challenges for very large-scale integration testing. This study presents a deterministic built-in self-test scheme using variable-length multiple linear feedback shift registers to generate the compressed low power test set. The experimental results show that both test power and test application time can be reduced significantly. View full abstract»

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  • Output remapping technique for critical paths soft-error rate reduction

    Page(s): 325 - 333
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (442 KB)  

    As technology scales, soft errors in deep submicron circuits have become a major reliability concern due to smaller node capacitances and lower supply voltages. It is expected that the soft error rate (SER) of combinational logic will increase significantly. Previous solutions to mitigate soft errors in combinational logic suffer from delay penalty or area/power overhead. The authors proposed here an output remapping technique to reduce SER of critical paths. The SER reduction of our method ranges from 59.2 to 89.8%. This method does not introduce any delay penalty in most cases. The area/power overhead is limited as well. The output remapping method is based on the trade-off between SER and gate delay. The analysis shows that the width of the particle strike induced glitch scales down with technology scaling, which guarantees that output remapping technique works well along with technology scaling. View full abstract»

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  • Design feasibility study for a 500 Gbits/s advanced encryption standard cipher/decipher engine

    Page(s): 334 - 348
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1232 KB)  

    A feasibility study for implementing the advanced encryption standard (AES) encryption algorithm in hardware achieving 500 Gbits/s is presented. Iterative processing cores are used to achieve the 500 Gbits/s. The throughput of the iterative cores is enhanced by processing four different flows of data in parallel. This does not increase the latency which is highly beneficial in the context of block cipher modes. The iterative core field-programmable gate array (FPGA) synthesis results in a throughput of 4.9 Gbits/s for an area of 6310 look-up tables (LUTs) outperforming several other contributions results. Several instances of the iterative processor are compared with pipelined architectures. The results have shown that for most implementations the group of iterative processors also outperforms pipelined architectures. The methodology followed in the process of obtaining the solution allowed us to reach a highly regular solution. The obtained architecture is highly modular and scalable. The key schedule generation is decoupled from the cipher/decipher engine. Block cipher mode datapath design is presented. The task of scheduling the different flows onto different iterative cores is realised through the use of a distributed scheduling architecture that implements a de-facto load balancing. View full abstract»

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IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems.

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