By Topic

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 7 • Date July 2010

Filter Results

Displaying Results 1 - 20 of 20
  • Table of contents

    Publication Year: 2010 , Page(s): C1
    Save to Project icon | Request Permissions | PDF file iconPDF (108 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2010 , Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (35 KB)  
    Freely Available from IEEE
  • Design Tools for Digital Microfluidic Biochips: Toward Functional Diversification and More Than Moore

    Publication Year: 2010 , Page(s): 1001 - 1017
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (903 KB) |  | HTML iconHTML  

    Microfluidics-based biochips enable the precise control of nanoliter volumes of biochemical samples and reagents. They combine electronics with biology, and they integrate various bioassay operations, such as sample preparation, analysis, separation, and detection. Compared to conventional laboratory procedures, which are cumbersome and expensive, miniaturized biochips offer the advantages of high... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files

    Publication Year: 2010 , Page(s): 1018 - 1027
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (584 KB) |  | HTML iconHTML  

    For embedded systems, where neither energy nor reliability can be easily sacrificed, this paper presents an energy efficient soft error protection scheme for register files (RFs). Unlike previous approaches, the proposed method explicitly optimizes for energy efficiency and can exploit the fundamental tradeoff between reliability and energy. While even simple compiler-managed RF protection scheme ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Tag Machine Based Performance Evaluation Method for Job-Shop Schedules

    Publication Year: 2010 , Page(s): 1028 - 1041
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (567 KB) |  | HTML iconHTML  

    This paper proposes a methodology for performance evaluation of schedules for job-shops modeled using tag machines. The most general tag structure for capturing dependences is shown to be inadequate for the task. A new tag structure is proposed. Comparison of the method with existing ones reveals that the proposed method has no dependence on schedule length in terms of modeling efficiency and it s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Time-Stepping Numerical Simulation of Switched Circuits Within the Nonsmooth Dynamical Systems Approach

    Publication Year: 2010 , Page(s): 1042 - 1055
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (539 KB) |  | HTML iconHTML  

    The numerical integration of switching circuits is known to be a tough issue when the number of switches is large, or when sliding modes exist. Then, classical analog simulators may behave poorly, or even fail. In this paper, it is shown on two examples that the nonsmooth dynamical systems (NSDS) approach, which is made of: 1) a specific modeling of the piecewise-linear electronic devices (ideal d... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks

    Publication Year: 2010 , Page(s): 1056 - 1069
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (444 KB) |  | HTML iconHTML  

    Artificial neural networks (ANNs) have shown great promise in modeling circuit parameters for computer aided design applications. Leakage currents, which depend on process parameters, supply voltage and temperature can be modeled accurately with ANNs. However, the complex nature of the ANN model, with the standard sigmoidal activation functions, does not allow analytical expressions for its mean a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power

    Publication Year: 2010 , Page(s): 1070 - 1082
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3710 KB) |  | HTML iconHTML  

    In sub-100nm CMOS processes, delay and leakage power reduction continue to be among the most critical design concerns. We propose to exploit the recent availability of fine-grain exposure dose control in the step-and-scan tool to achieve both design-time (placement) and manufacturing-time (yield-aware dose mapping) optimizations of timing yield and leakage power. Our placement and dose map co-opti... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Decision-Theoretic Design Space Exploration of Multiprocessor Platforms

    Publication Year: 2010 , Page(s): 1083 - 1095
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (678 KB) |  | HTML iconHTML  

    This paper presents an efficient technique to perform design space exploration of a multiprocessor platform that minimizes the number of simulations needed to identify a Pareto curve with metrics like energy and delay. Instead of using semi-random search algorithms (like simulated annealing, tabu search, genetic algorithms, etc.), we use the domain knowledge derived from the platform architecture ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form

    Publication Year: 2010 , Page(s): 1096 - 1109
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (707 KB) |  | HTML iconHTML  

    An optimal linear-time algorithm for interprocedural register allocation in high level synthesis is presented. Historically, register allocation has been modeled as a graph coloring problem, which is nondeterministic polynomial time-complete in general; however, converting each procedure to static single assignment (SSA) form ensures a chordal interference graph, which can be colored in O(V + E) t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On Reducing Scan Shift Activity at RTL

    Publication Year: 2010 , Page(s): 1110 - 1120
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (5059 KB) |  | HTML iconHTML  

    Power dissipation in digital circuits during scan-based test is generally much higher than that during functional operation. Unfortunately, this increased test power can create hot spots that may damage the silicon, the bonding wires, and even the package. It can also cause intensive erosion of conductors-severely decreasing the reliability of a device. Finally, excessive test power may also resul... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Computation of Intermodulation Distortion in RF Circuits Using Single-Tone Moments Analysis

    Publication Year: 2010 , Page(s): 1121 - 1125
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1009 KB) |  | HTML iconHTML  

    Obtaining the value of the third order intercept point using traditional simulation techniques typically requires a nonlinear steady state analysis with multitone inputs, which is very computationally expensive. In this paper, a new method is presented for the computation of the third order intercept point. Using the proposed approach, the necessary Volterra kernels are computed directly from the ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Incremental Solving Techniques for SAT-based ATPG

    Publication Year: 2010 , Page(s): 1125 - 1130
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1494 KB) |  | HTML iconHTML  

    Automatic test pattern generation (ATPG) based on the Boolean satisfiability (SAT) problem has recently been proven to be a beneficial complement to traditional methods. Efficient SAT techniques yield a robust fault classification. In this paper, we present methodologies to improve the efficiency of SAT-based ATPG. First, we give a detailed run time analysis of a state-of-the-art SAT-based ATPG to... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • EOF: Efficient Built-In Redundancy Analysis Methodology With Optimal Repair Rate

    Publication Year: 2010 , Page(s): 1130 - 1135
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (4050 KB) |  | HTML iconHTML  

    Faulty cell repair with redundancy can improve memory yield. In particular, built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. We propose an efficient BIRA algorithm to achieve the optimal repair rate with a very short analysis time and low hardware cost. The proposed algorithm can significantly reduce the number of backtracks in the exhaustive search alg... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits

    Publication Year: 2010 , Page(s): 1135 - 1140
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (287 KB) |  | HTML iconHTML  

    We demonstrate that undetectable single stuck-at faults in full-scan benchmark circuits tend to cluster in certain areas. This implies that certain areas may remain uncovered by a test set for single stuck-at faults. We describe an extension to the set of target faults aimed at providing a better coverage of the circuit in the presence of undetectable single stuck-at faults. The extended set of ta... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automated Model Generation Algorithm for High-Level Fault Modeling

    Publication Year: 2010 , Page(s): 1140 - 1145
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2720 KB) |  | HTML iconHTML  

    High-level modeling for operational amplifiers (opamps) has been previously carried out successfully using models generated by published automated model generation approaches. Furthermore, high-level fault modeling (HLFM) has been shown to work reasonably well using manually designed fault models. However, no evidence shows that published automated model generation approaches based on opamps have ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Special issue on reliable embedded computing

    Publication Year: 2010 , Page(s): 1146
    Save to Project icon | Request Permissions | PDF file iconPDF (589 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2010 , Page(s): 1147
    Save to Project icon | Request Permissions | PDF file iconPDF (25 KB)  
    Freely Available from IEEE
  • Explore IEL IEEE's most comprehensive resource [advertisement]

    Publication Year: 2010 , Page(s): 1148
    Save to Project icon | Request Permissions | PDF file iconPDF (345 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2010 , Page(s): C3
    Save to Project icon | Request Permissions | PDF file iconPDF (33 KB)  
    Freely Available from IEEE

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu