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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 6 • Date June 2010

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  • Table of contents

    Publication Year: 2010 , Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Publication Year: 2010 , Page(s): C2
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  • Micropower Data Converters: A Tutorial

    Publication Year: 2010 , Page(s): 405 - 410
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (532 KB) |  | HTML iconHTML  

    In many applications, such as in battery-operated medical devices or in habitat monitoring sensor networks, special data converters are needed, which can operate on battery or even harvested power. The available power in these devices is very limited, often only a few tens of microwatts. This tutorial discusses some of the design options for such micropower digital-to-analog and analog-to-digital converters. View full abstract»

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  • A CMOS Outphasing Power Amplifier With Integrated Single-Ended Chireix Combiner

    Publication Year: 2010 , Page(s): 411 - 415
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (493 KB) |  | HTML iconHTML  

    This brief proposes an on-chip outphasing power amplifier that uses a single-ended Chireix combiner for a linear amplification with a nonlinear component amplifier. The proposed combiner structure consists of a lumped inductor and a lumped capacitor that can achieve the simple single-ended configuration of a Chireix combiner. It is also suitable for on-chip implementation with minimum efficiency deterioration. An inductance-capacitance balun using the lumped model of λ/4 and 3λ/4 transmission lines was effectively merged into a simple Chireix combiner for two outphased input signals. The relation between the output resistance and the outphasing angle of the input signals was derived to determine the maximum efficiency. A voltage-mode class-D power amplifier was used with the combiner to illustrate the combiner's effectiveness. The prototype fabricated in a 0.13-μm complementary metal-oxide-semiconductor process shows a maximum 52% power-added efficiency (continuous wave) and a -47-dBc adjacent channel power ratio performance at a 10-MHz offset with a 1.92-GHz wideband code-division multiple-access signal. View full abstract»

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  • The Nyquist Criterion: A Useful Tool for the Robust Design of Continuous-Time \Sigma \Delta Modulators

    Publication Year: 2010 , Page(s): 416 - 420
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (278 KB) |  | HTML iconHTML  

    In this brief, we introduce a figure of merit for the robustness of continuous-time (CT) ΣΔ modulators. It is based on the Nyquist criterion for the equivalent discrete-time loop filter. We show how CT modulators can be designed by optimizing this figure of merit. This way, we obtain modulators with increased robustness against variations in the noise-transfer-function (NTF) parameters. This is particularly useful for constrained systems, where the system order exceeds the number of design parameters. This situation occurs, for example, due to the effect of the excess loop delay or the finite gain bandwidth of the operational amplifiers. Additionally, it is shown that the optimization is equivalent to the minimization of H, which is the maximum out-of-band gain of the NTF. This explains why conventional design strategies that are based on H, such as Schreier's approach, provide quite robust modulator designs in the case of unconstrained architectures. View full abstract»

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  • An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL

    Publication Year: 2010 , Page(s): 421 - 425
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (586 KB) |  | HTML iconHTML  

    This brief proposes a novel circuit architecture of an 11-bit reversible successive approximation register (RSAR)controlled all-digital delay-locked loop (DLL), which could achieve adaptive bandwidth in a wide operation range by utilizing the modified binary search algorithm of the RS AR scheme. Moreover, it is fast locking because it finds the suitable delay range first and the successive approximation register process next. The proposed RSAR DLL is fabricated into a 0.2 × 0.1 mm2 silicon with SMIC 0.13-μm 1P6M complimentary metal-oxide-semiconductor technology. Test shows that the chip could work in a wide frequency range from 30 MHz to 1 GHz, with less than 42 cycles lock-in time, 10-ps delay resolution, and 1.5 mW at 30-MHz power dissipation. View full abstract»

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  • Sampling and Reconstruction of Transient Signals by Parallel Exponential Filters

    Publication Year: 2010 , Page(s): 426 - 429
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (114 KB) |  | HTML iconHTML  

    This brief introduces a new method for sampling of transient analog waveforms based on the parallel exponential filters. The signal is fed to the parallel network consisting of resistor-capacitor (RC) circuits, outputs of which are simultaneously sampled. We show that N previous samples of the input signal can be reconstructed from single output samples of N parallel RC circuits. The parallel sampling method increases the sampling rate of the data acquisition system by a factor of N. In particular, the method is useful in increasing the sampling rate of the Flash-type analog-to-digital VLSI circuits. We present the parallel RC network, develop the reconstruction algorithm, and briefly describe a variety of applications such as measurement and reconstruction of pulses produced by ultrawideband transmitters, radiation detectors, and pulse lasers. View full abstract»

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  • A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm

    Publication Year: 2010 , Page(s): 430 - 434
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (812 KB) |  | HTML iconHTML  

    This brief presents a frequency estimation algorithm (FEA) for an all-digital phase-locked loop (ADPLL) instead of the traditional binary frequency-searching algorithm. Based on the proposed FEA and a new fast-lock scheme, a fast-lock engine is designed to improve the lock-in time of an ADPLL design with two referenced clock cycles. An implementation of the proposed ADPLL design is realized by utilizing United Microelectronics Corporation (UMC) 0.18-μm 1P6M CMOS technology with a core area of 300 × 250 μm2, consisting of an acceptable input reference clock ranging from 220 kHz to 8 MHz. The ADPLL design has a frequency range of 28-446 MHz with an 8.8-ps digitally controlled oscillator resolution. Moreover, the peak-to-peak jitter of the ADPLL achieves 70 ps, respectively. View full abstract»

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  • A Power-Efficient Voltage Upconverter for Embedded EEPROM Application

    Publication Year: 2010 , Page(s): 435 - 439
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (425 KB) |  | HTML iconHTML  

    This brief presents a power-efficient voltage upconverter applicable to a mobile electrically erasable programmable read-only memory (EEPROM). The power dissipation is reduced by optimizing the three constituent blocks: the CMOS-type Dickson's charge pump, the level detector for the boosted power supply (V P P), and the level shifter. The power consumption of the V P P level detector is greatly reduced by employing an RC coupled voltage divider. The short-circuit current of the level shifter is eliminated by bootstrapping the gate nodes of stacked protection PMOSFETs. The voltage upconverter is implemented into a 768-bit EEPROM using 0.18-m CMOS technology and dissipates about 20.2 W for regulation and consumption of V P P. View full abstract»

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  • A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing

    Publication Year: 2010 , Page(s): 440 - 445
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (720 KB) |  | HTML iconHTML  

    The access timing control of low-voltage static random access memory cells encounters crucial challenges in the presence of within-die (WID) variations, which induce severe delay mismatches between the timing-reference circuit and the bitlines. Prevention of early activation of sense amplifiers (SAs) is thus required to improve the yield. This brief proposes a novel SA-activation scheme by sensing differential bitlines locally and concurrently. The proposed structure effectively tolerates the WID variations and supports dynamic voltage scaling down to the subthreshold supply voltage. Measurement results show that the fabricated 8-kb test chips using 90-nm technology can be operated at the supply voltage range from 1 V (nominal Vdd) to 0.16 V. The maximum operating frequency at 0.16 V is up to 200 kHz. View full abstract»

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  • Low Hardware Complexity Pipelined Rank Filter

    Publication Year: 2010 , Page(s): 446 - 450
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (443 KB) |  | HTML iconHTML  

    The major benefit of a disclosed low-hardware-complexity pipelined rank filter is reduction in hardware complexity and increase in processing speed, due to identical pipelined stages and the absence of mask bits. Field-programmable-gate-array realization of this filter significantly reduces the number of used logic elements and registers, in comparison with the best prior art methods, and, at the same time, increases the maximum operating frequency. One rank-sample result is available at the output on each clock cycle, thus enabling real-time nonlinear image processing. View full abstract»

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  • A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications

    Publication Year: 2010 , Page(s): 451 - 455
    Cited by:  Papers (31)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (909 KB) |  | HTML iconHTML  

    This brief presents a fast Fourier transform (FFT) processor that provides high throughput rate (T.R.) by applying the eight-data-path pipelined approach for wireless personal area network applications. The hardware costs, including the power consumption and area, increase due to multiple data paths and increased wordlength along stages. To resolve these issues, a novel simplification method to reduce the hardware cost in multiplication units of the multiple-path FFT approach is proposed. A multidata scaling scheme to reduce wordlengths while preserving the signal-to-quantization-noise ratio is also presented. Using UMC 90-nm 1P9M technology, a 2048-point FFT processor test chip has been designed, and its 128-point FFT kernel has been fabricated for ultrawideband (UWB) applications and also for verification. The 2048-point FFT processor can provide a T.R. of 2.4 GS/s at 300 MHz with a power consumption of 159 mW. Compared with the four-data-path approach, a power consumption saving of about 30% can be achieved under the same T.R. In addition, the 128-point FFT kernel test chip has a measured power consumption of 6.8 mW with a T.R. of 409.6 MS/s at 52 MHz to meet the UWB standard with a saving in power consumption of about 40%. View full abstract»

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  • Effects of Current Time-Delayed Feedback on the Dynamics of a Permanent-Magnet Synchronous Motor

    Publication Year: 2010 , Page(s): 456 - 460
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (262 KB) |  | HTML iconHTML  

    We investigate how the dynamics of a permanent-magnet synchronous motor (PMSM) depends on current time-delayed feedback, in which the delay time is both fixed and varying in time. We choose model parameters for which the PMSM displays, in the absence of feedback, chaotic oscillations. The stable operation islands of the PMSM are first investigated in the parameter space of feedback gain and delay time. Then, detailed regimes of motion can be explored by bifurcation diagrams. It is found that the dynamic delay time feedback can obtain stabilization of unstable steady states over a much larger domain of parameters in comparison with the static delay time feedback. The mechanism behind the action of current time-delayed feedback is also addressed. This brief may provide a useful tip for maintaining the security operation of electromechanical systems. View full abstract»

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  • Blind Source Separation of Continuous-Time Chaotic Signals Based on Fast Random Search Algorithm

    Publication Year: 2010 , Page(s): 461 - 465
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (221 KB) |  | HTML iconHTML  

    Blind source separation (BSS) of continuous-time chaotic signals from a linear mixture is addressed in this brief. It is assumed that the functional forms of the generating systems of chaotic signals are known, and the parameters of the generating systems and the mixture matrix are unknown. The problem of determining the parameters and the mixture matrix is formulated as an optimization one. A fast random search (FRS) algorithm is, therefore, proposed. Experimental results demonstrate that the FRS algorithm can solve the indeterminacy problem in BSS and show the separability of mixed signals in a high noise background. View full abstract»

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  • Consideration of Volterra Series With Excitation and/or Impulse Responses in the Form of Dirac Impulses

    Publication Year: 2010 , Page(s): 466 - 470
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (98 KB) |  | HTML iconHTML  

    In this brief, the possible extensions of the Volterra series and also incorporating Dirac impulses in it are discussed. It is shown that two of them are valid, but the third one, in the usual sense, is not. These extensions form associated models, which are very helpful in the simplification of some calculations in the nonlinear analysis of systems described by the Volterra series. View full abstract»

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  • Some New Developments on the Al-Alaoui and the Pei and Hsu s-to-z Transforms

    Publication Year: 2010 , Page(s): 471 - 475
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB) |  | HTML iconHTML  

    This brief refocuses on three classes of s-to-z transforms. For each class, a closed-form expression is proposed, and a particular element, having an imaginary part of its frequency response very close to the ideal value, is presented. These s-to-z transforms are then related to all-pass infinite-impulse-response fractional delay filters, allowing another way to choose their degree of freedom. View full abstract»

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  • A Variable Regularization Method for Affine Projection Algorithm

    Publication Year: 2010 , Page(s): 476 - 480
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (407 KB) |  | HTML iconHTML  

    The affine projection algorithm (APA) is a generalization of the normalized least mean square algorithm. We propose a variable regularization factor for the APA. Instead of the conventional assumption that the a posteriori error is zero, we incorporate the statistical characteristic of the noise into the adaptation process based on a system identification setup. Exact and approximate formulations for the optimal regularization factor are derived. Numerical simulation results show that the proposed algorithm improves the performance of the APA in terms of its convergence rate and steady-state misalignment. View full abstract»

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  • Predictive Controller Design of Networked Systems With Communication Delays and Data Loss

    Publication Year: 2010 , Page(s): 481 - 485
    Cited by:  Papers (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (177 KB) |  | HTML iconHTML  

    This brief studies the predictive controller design of networked systems with communication delay and data loss. A networked predictive control scheme is employed to compensate for communication delay and data loss actively rather than passively. Based on analysis of the closed-loop networked predictive control systems, a design strategy of the predictive controller is proposed. The designed predictive controller can achieve the desired control performance and also guarantee the system stability. A numerical example demonstrates the compensation for communication delay and data loss in networked systems using the proposed predictive controller design strategy. View full abstract»

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  • Passivity Analysis of Uncertain Singularly Perturbed Systems

    Publication Year: 2010 , Page(s): 486 - 490
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (119 KB) |  | HTML iconHTML  

    This brief addresses the asymptotic stability and passivity of uncertain singularly perturbed systems. Based on the Lyapunov stability theory and a singular-system approach, some sufficient conditions in terms of linear matrix inequalities are derived. Three numerical examples are presented to demonstrate the effectiveness of the proposed theoretical results. View full abstract»

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  • In Memoriam

    Publication Year: 2010 , Page(s): 491 - 492
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  • Why we joined ... [advertisement]

    Publication Year: 2010 , Page(s): 493
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  • IEEE 2009 Membership Application

    Publication Year: 2010 , Page(s): 494 - 495
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

    Publication Year: 2010 , Page(s): 496
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2010 , Page(s): C3
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    Freely Available from IEEE

Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope