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Industrial Electronics, IEEE Transactions on

Issue 7 • Date July 2010

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Displaying Results 1 - 25 of 41
  • Table of contents

    Page(s): C1 - 2193
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  • IEEE Transactions on Industrial Electronics publication information

    Page(s): C2
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  • Guest Editorial

    Page(s): 2194 - 2196
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  • A Survey on Cascaded Multilevel Inverters

    Page(s): 2197 - 2206
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (415 KB) |  | HTML iconHTML  

    Cascaded multilevel inverters synthesize a medium-voltage output based on a series connection of power cells which use standard low-voltage component configurations. This characteristic allows one to achieve high-quality output voltages and input currents and also outstanding availability due to their intrinsic component redundancy. Due to these features, the cascaded multilevel inverter has been recognized as an important alternative in the medium-voltage inverter market. This paper presents a survey of different topologies, control strategies and modulation techniques used by these inverters. Regenerative and advanced topologies are also discussed. Applications where the mentioned features play a key role are shown. Finally, future developments are addressed. View full abstract»

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  • Survey on Fault Operation on Multilevel Inverters

    Page(s): 2207 - 2218
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    This paper is related to faults that can appear in multilevel (ML) inverters, which have a high number of components. This is a subject of increasing importance in high-power inverters. First, methods to identify a fault are classified and briefly described for each topology. In addition, a number of strategies and hardware modifications that allow for operation in faulty conditions are also presented. As a result of the analyzed works, it can be concluded that ML inverters can significantly increase their availability and are able to operate even with some faulty components. View full abstract»

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  • A Survey on Neutral-Point-Clamped Inverters

    Page(s): 2219 - 2230
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1163 KB) |  | HTML iconHTML  

    Neutral-point-clamped (NPC) inverters are the most widely used topology of multilevel inverters in high-power applications (several megawatts). This paper presents in a very simple way the basic operation and the most used modulation and control techniques developed to date. Special attention is paid to the loss distribution in semiconductors, and an active NPC inverter is presented to overcome this problem. This paper discusses the main fields of application and presents some technological problems such as capacitor balance and losses. View full abstract»

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  • Modeling and DBC-PSC-PWM Control of a Three-Phase Flying-Capacitor Stacked Multilevel Voltage Source Inverter

    Page(s): 2231 - 2239
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (912 KB) |  | HTML iconHTML  

    In this paper, the authors propose a mathematical model for a new topology called "stacked multicell converter" (SMC). Each phase of the SMC n × m multilevel inverter is formed by a stack of m flying-capacitor multilevel inverters, and each stack or stage is realized by connecting in series n controllable commutation cells. An original multicarrier subharmonic pulsewidth modulation (PWM), called disposition band carrier and phase-shifted carrier PWM (DBC-PSC-PWM), method is developed to produce (n × m + 1) output voltage levels and to improve the output voltage harmonic spectrum with a wide output frequency range. A diagram state machine is then used to decode the DBC-PSC-PWM modulator and distribute the commutations evenly to each inverter cell in a cyclical fashion. To carry out, in practice, the SMC n × m modulation technique, the implementation of the modulation control strategy has been done in a field-programmable gate array circuit XC4010E+ of XILINX to control a three-phase SMC 3 × 2 seven-level inverter, and the experimental results are carried out to confirm the high performance of this inverter. View full abstract»

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  • Direct Control Strategy for a Four-Level Three-Phase Flying-Capacitor Inverter

    Page(s): 2240 - 2248
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1825 KB) |  | HTML iconHTML  

    A direct predictive control strategy is proposed for a three-phase four-level flying-capacitor (FC) inverter in this paper. The balancing of the FC voltages, a challenge in applications with small capacitors and low switching frequencies, is done without any modulation, simply using tables calculated offline. These allow the realization of fast-dynamics output currents with reduced dv/dt in the output voltages and reduced switching frequencies. Moreover, no interharmonics are created when operating at low switching frequencies and with reference currents containing multiple harmonic components, which is a key feature for active power filters. Simulations and experimental results are presented to demonstrate the excellent performance of the direct control strategy in comparison with a conventional pulsewidth-modulation control technique, mostly for operation at low switching frequencies. View full abstract»

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  • Flying-Capacitor-Based Chopper Circuit for DC Capacitor Voltage Balancing in Diode-Clamped Multilevel Inverter

    Page(s): 2249 - 2261
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (939 KB) |  | HTML iconHTML  

    This paper proposes a flying-capacitor-based chopper circuit for dc capacitor voltage equalization in diode-clamped multilevel inverters. Its important features are reduced voltage stress across the chopper switches, possible reduction in the chopper switching frequency, improved reliability, and ride-through capability enhancement. This topology is analyzed using three- and four-level flying-capacitor-based chopper circuit configurations. These configurations are different in capacitor and semiconductor device count and correspondingly reduce the device voltage stresses by half and one-third, respectively. The detailed working principles and control schemes for these circuits are presented. It is shown that, by preferentially selecting the available chopper switch states, the dc-link capacitor voltages can be efficiently equalized in addition to having tightly regulated flying-capacitor voltages around their references. The various operating modes of the chopper are described along with their preferential selection logic to achieve the desired performances. The performance of the proposed chopper and corresponding control schemes are confirmed through both simulation and experimental investigations. View full abstract»

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  • Analysis and Calculation of Zero-Sequence Voltage Considering Neutral-Point Potential Balancing in Three-Level NPC Converters

    Page(s): 2262 - 2271
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    The neutral-point (NP) potential of the three-level neutral-point-clamped converters is needed to maintain balancing. Zero-sequence voltage is the only freedom degree when carrier-based pulsewidth modulation is utilized. Appropriate zero-sequence voltage should be identified to control the NP potential. The relationship between the neutral current and injected zero-sequence voltage is studied comprehensively, and two balancing algorithms of NP potential, respectively adopting searching-optimization and interpolation methods, are presented. The theoretical optimum zero-sequence voltage for controlling NP potential can be obtained by the latter proposed algorithm. Simulation and experimental results are shown to verify the validity and practicability of the proposed algorithms. View full abstract»

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  • New Active Stacked NPC Multilevel Converter: Operation and Features

    Page(s): 2272 - 2278
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1385 KB) |  | HTML iconHTML  

    In this paper, the operation and the features of a new three-level converter are presented. The proposed topology was named three-level active-stacked neutral point clamped (3L-ASNPC). It is a derivative of the 3L-SNPC structure, having two additional active switches connected antiparallel with the clamp diodes. The main advantage of 3L-ASNPC converter is the reduction of the average switching frequency for all power devices. In the same time, the apparent switching frequency of the output voltage is doubled. Experimental and simulation results are shown in order to validate the proposed structure and the analysis of the switching states. View full abstract»

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  • The Common Cross-Connected Stage for the 5L ANPC Medium Voltage Multilevel Inverter

    Page(s): 2279 - 2286
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1627 KB) |  | HTML iconHTML  

    Rising interest in multilevel applications has triggered new research activities. This paper proposes a novel multilevel power electronics building block (PEBB) for the five-level active neutral point clamped (ANPC) multilevel voltage source inverter. The PEBB is composed of six switches in a crossed configuration and one capacitor. It is common to the three phases of a five-level ANPC topology, enabling a large number of levels to be generated. This PEBB is meant to be a reliable upgrade to the 5L topology, increasing output signal quality and reducing the size of the output filter in medium voltage applications. The number of levels generated by the common cross-connected stage (C3S) PEBB and the ANPC depends on the voltage ratios chosen between the phase capacitors of the ANPC and the PEBB capacitor(s). The tradeoff stands between the ability to balance the capacitors, the rated blocking voltage of the devices, and the number of levels produced. Under a given configuration, nine levels can be produced, with the possibility to balance the capacitors up to modulation indexes in the region of m = 0.92. The analysis of the general topology, the description of the nine-level case, and simulation results are first presented. Prototyping results are then shown, and they validate the introduced concept and topology. View full abstract»

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  • Analysis of the Power Balance in the Cells of a Multilevel Cascaded H-Bridge Converter

    Page(s): 2287 - 2296
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    Multilevel cascaded H-bridge (CHB) converters have been presented as a good solution for high-power applications. In this way, several control and modulation techniques have been proposed for this power converter topology. In this paper, the steady-state power balance in the cells of a single-phase two-cell CHB is studied. The capability to be supplied with active power from the grid or to deliver active power to the grid in each cell is analyzed according to the dc-link voltages and the desired ac output voltage value. The limits of the maximum and minimum input active powers for a stable operation of the CHB are addressed. Simulation results are shown to validate the presented analysis. View full abstract»

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  • Comparison of Neutral-Point-Clamped, Symmetrical, and Hybrid Asymmetrical Multilevel Inverters

    Page(s): 2297 - 2306
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (876 KB) |  | HTML iconHTML  

    This paper presents a comparison of three topologies of multilevel inverters applied to drive an induction motor of 500 kVA/4.16 kV rating. The multilevel inverters analyzed are the following: a neutral-point-clamped inverter, a symmetrical cascaded multilevel inverter, and a hybrid asymmetrical cascaded multilevel inverter. The performance indexes used in the comparison are total harmonic distortion, first-order distortion factor, second-order distortion factor, common-mode voltage, semiconductor power loss distribution, and heat-sink volume. The multilevel inverters are designed to present 99% efficiency at the nominal operating point, and the aforementioned performance indexes are compared for distinct values of amplitude modulation depth. View full abstract»

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  • Symmetrical Hybrid Multilevel DC–AC Converters With Reduced Number of Insulated DC Supplies

    Page(s): 2307 - 2314
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1397 KB) |  | HTML iconHTML  

    Novel symmetric hybrid multilevel topologies are introduced for both single- and three-phase medium-voltage high-power systems. The topology conception is presented in detail, where a three-level switching cell with low component count, and its modulation pattern give the origin of the proposed converters. Voltage sharing and low output-voltage distortion are achieved. The theoretical frequency spectra are derived. Switching devices are separated into high- and low-frequency devices, generating hybrid converters. Five-level three-phase topologies are generated from only three insulated dc sources, while the number of semiconductors is the same as for the cascaded H bridge. Both simulation and experimental results are provided showing the validity of the analysis. View full abstract»

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  • Selective Harmonic Mitigation Technique for High-Power Converters

    Page(s): 2315 - 2323
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    In high-power applications, the maximum switching frequency is limited due to thermal losses. This leads to highly distorted output waveforms. In such applications, it is necessary to filter the output waveforms using bulky passive filtering systems. The recently presented selective harmonic mitigation pulsewidth modulation (SHMPWM) technique produces output waveforms where the harmonic distortion is limited, fulfilling specific grid codes when the number of switching angles is high enough. The related technique has been previously presented using a switching frequency that is equal to 750 Hz. In this paper, a special implementation of the SHMPWM technique optimized for very low switching frequency is studied. Experimental results obtained applying SHMPWM to a three-level neutral-point-clamped converter using a switching frequency that is equal to 350 Hz are presented. The obtained results show that the SHMPWM technique improves the results of previous selective harmonic elimination pulsewidth modulation techniques for very low switching frequencies. This fact highlights that the SHMPWM technique is very useful in high-power applications, leading its use to an important reduction of the bulky and expensive filtering elements. View full abstract»

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  • Three-Dimensional Space-Vector Modulation to Reduce Common-Mode Voltage for Multilevel Inverter

    Page(s): 2324 - 2331
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (937 KB) |  | HTML iconHTML  

    In this paper, an approach to reduce common-mode voltage (CMV) at the output of multilevel inverter using 3-D space-vector modulation (SVM) is proposed. The 3-D SVM is superset of the traditional 2-D SVM, and thus, it inherits all the merits of traditional 2-D. A simple technique for the selection of switching states to constitute the reference vector is proposed here. The computational cost of the proposed technique is independent of voltage levels of inverter. This technique is easy to implement online in digital controller. The tradeoff between quality of output voltage and CMV is achieved in this paper. This paper realizes the implementation of 3-D SVM to reduce the CMV using a five-level diode-clamped inverter for a three-phase induction motor. Experimental and simulation results demonstrate the feasibility of the proposed technique. View full abstract»

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  • A Space Vector Switching Strategy for Three-Level Five-Phase Inverter Drives

    Page(s): 2332 - 2343
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    A novel space vector modulation (SVM) technique for a three-level five-phase inverter is described based on an optimized five vectors concept. The concept utilizes a novel vector minimization technique that reduces the number of vectors in the d1-q1 vector space by identifying candidate vectors in each of the ten sectors that comprise the decagon vector space. The candidate vectors are selected based on the inequality relationship between the five-phase voltages during each switching cycle. Using this technique, the original 243 inverter states are reduced to 113 candidate vectors, and from the remaining states ten possible switching sequences in each sector are utilized to develop the desired voltage reference in the d1-q1 vector space while forcing a null vector in the d3-q3 vector space. A novel region determination technique is also introduced to identify the subregion that the d1-q1 voltage vector occupies. This technique significantly reduces the computational overhead required when implementing SVM techniques with multilevel and multiphase inverters. The space vector technique can utilize redundant vectors to assist in balancing subcycle variation of the dc-link capacitor voltage under unbalanced load conditions. Experiments validate simulation results where the low-order voltage harmonics show that the d3-q3 voltage vector is null. View full abstract»

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  • Multiband Hysteresis Modulation and Switching Characterization for Sliding-Mode-Controlled Cascaded Multilevel Inverter

    Page(s): 2344 - 2353
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (718 KB) |  | HTML iconHTML  

    In this paper, a generalized multiband hysteresis modulation and its characterization have been proposed for the sliding-mode control of cascaded H-bridge multilevel-inverter (CHBMLI)-controlled systems. A frequency-domain method is proposed for the determination of net hysteresis bandwidth for a given desired maximum switching frequency of the inverter. The switching transition concept of Tsypkin's method and the describing function of nonlinear relay have been used for the derivation of results. A hierarchical switching algorithm has been suggested for the modular cells of the cascaded multilevel inverter. The hierarchy of each cell is swapped sequentially to provide the self-balancing capability in case the dc-link voltage is supported by the capacitors. The simulation and experimental verification of the derived results are provided through a single-phase distribution static compensator (DSTATCOM) model. The application in the three-phase system has been shown through simulation studies on a 3.3-kV distribution-system compensation using DSTATCOM. Verification on both single- and three-phase systems is obtained using a five-level cascaded-multilevel-inverter topology. View full abstract»

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  • A New Space-Vector PWM With Optimal Switching Selection for Multilevel Coupled Inductor Inverters

    Page(s): 2354 - 2364
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2073 KB) |  | HTML iconHTML  

    Multilevel space vector pulsewidth modulation (SVPWM) control is shown to be a very useful tool for coupled inductor inverters as six independent pulsewidth modulation (PWM) signals are required, and there is additional complexity of meeting the performance requirements for the coupled inductor while balancing the winding common-mode dc current and generating high-quality multilevel PWM output voltages. A new multilevel SVPWM technique with a five-segment switching sequence is described, where half-wave symmetrical PWM voltage waveforms are used to balance the inductor common-mode dc voltages and also to avoid all possible switching states with a high winding current ripple. The proposed SVPWM is shown to have better inverter performance, compared with traditional carrier-based and the original multilevel SVPWM schemes at low modulation depths. Inverter operation with the proposed SVPWM is validated through simulation and experimental results. View full abstract»

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  • A Novel PWM Control Method for Hybrid-Clamped Multilevel Inverters

    Page(s): 2365 - 2373
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (643 KB) |  | HTML iconHTML  

    A novel pulsewidth modulation (PWM) control method is proposed in this paper. The PWM control method is called higher and lower carrier cells alternative phase opposition PWM (HLCCAPOPWM) for the hybrid-clamped multilevel inverter and based on the improvement of carrier phase disposition PWM (PDPWM). The principle of the HLCCAPOPWM method, the comparison with the carrier PDPWM method, and the analysis on output voltage spectrum are given. Simulations and experiments show that comparing with the carrier PDPWM method, the novel method can effectively reduce the number of devices switching on or off within broad modulation index range, consequently reducing switching losses, and remarkably reduce the amplitude of lower harmonics. Simulations also show the generalization of the HLCCAPOPWM method for hybrid-clamped n-level inverters and neutral-point-clamped inverters. View full abstract»

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  • Synchronous Optimal Pulsewidth Modulation for Low-Switching-Frequency Control of Medium-Voltage Multilevel Inverters

    Page(s): 2374 - 2381
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    This paper presents the mechanism and details of synchronous optimal pulsewidth modulation (PWM) generation for control of medium-voltage induction motor drives using multilevel inverters at low switching frequency. Multilevel inverters allow operation at multiple of dc-link voltage and reduce the total harmonic distortion (THD). Synchronous optimal PWM control permits setting the maximum switching frequency to a low value without compromising THD. Low switching frequency reduces the switching losses of the power semiconductor devices. An optimal control procedure is explained in detail. The performances of three- and five-level inverter topologies are compared. The experimental results of a five-level inverter drive using optimal PWM control are presented. View full abstract»

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  • Complete Fast Analytical Solution of the Optimal Odd Single-Phase Multilevel Problem

    Page(s): 2382 - 2397
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    In this paper, we focus on the computation of optimal switching angles for general multilevel (ML) odd symmetry waveforms. We show that this problem is similar to (but more general than) the optimal pulsewidth modulation (PWM) problem, which is an established method of generating PWM waveforms with low baseband distortion. We introduce a new general modulation strategy for ML inverters, which takes an analytic form and is very fast, with a complexity of only O(n log2 n) arithmetic operations, where n is the number of controlled harmonics. This algorithm is based on a transformation of appropriate trigonometric equations for each controlled harmonics to a polynomial system of equations that is further transformed to a special system of composite sum of powers. The solution of this system is carried out by a modification of the Newton's identity via Padé approximation, formal orthogonal polynomials (FOPs) theory, and properties of symmetric polynomials. Finally, the optimal switching sequence is obtained by computing zeros of two FOP polynomials in one variable or, alternatively, by a special recurrence formula and eigenvalues computation. View full abstract»

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  • Evaluation of a Multilevel Cascaded-Type Dynamic Voltage Restorer Employing Discontinuous Space Vector Modulation

    Page(s): 2398 - 2410
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1956 KB) |  | HTML iconHTML  

    In this paper, the application of a cascaded multilevel inverter as a dynamic voltage restorer (DVR) is investigated. Two discontinuous multilevel space vector modulation (SVM) techniques are implemented for DVR control and are shown to reduce inverter switching losses while maintaining virtually the same harmonic performance as the conventional multilevel SVM at a high number of levels. This paper also presents a mathematical relationship for computing the distortion at the point of common coupling (PCC) as a function of the distortion of the DVR. This enables the selection of the number of levels required for a certain application. An extended sag duration support compared to the two-level DVR is another advantage of the DVR with a cascaded multilevel inverter. The common-mode voltage (CMV) at the PCC has been evaluated for the three SVM techniques (the conventional multilevel SVM and the two discontinuous SVM), presenting a lower CMV for the second discontinuous SVM. A design example is presented for an 11-kV 5-MVA DVR multilevel cascaded inverter for up to 17 levels, employing the conventional multilevel SVM and the two discontinuous SVM techniques. View full abstract»

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  • Asymmetrical Cascade Multilevel Converters With Noninteger or Dynamically Changing DC Voltage Ratios: Concepts and Modulation Techniques

    Page(s): 2411 - 2418
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    Asymmetrical cascade multilevel inverters offer a high number of voltage levels with a given switch count. For a given topology, the number of levels depends on the configuration of the dc voltage (ratios). This paper deals with the design and control of such converters with noninteger dc voltage ratio, which leads to unevenly distributed space vectors. It describes how to select the dc voltage ratio configurations that yield space vectors as evenly distributed as possible. It describes how to produce an effective PWM modulation that allows generating undistorted current even in the presence of (some) unevenly distributed space vectors. View full abstract»

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Aims & Scope

IEEE Transactions on Industrial Electronics encompasses the applications of electronics, controls and communications, instrumentation and computational intelligence for the enhancement of industrial and manufacturing systems and processes.

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Meet Our Editors

Editor-in-Chief
Carlo Cecati
DISIM - Univ. degli Studi dell'Aquila
67100 Aquila, Italy
c.cecati@ieee.org
Phone: +39 0862 434 450
Fax: +39 0862 1960 411