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IEEE Computer Architecture Letters

Issue 1 • Jan. 2010

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Displaying Results 1 - 13 of 13
  • [Front cover]

    Publication Year: 2010, Page(s): c1
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  • Editorial Board [Cover2]

    Publication Year: 2010, Page(s): c2
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  • Using Resampling Techniques to Compute Confidence Intervals for the Harmonic Mean of Rate-Based Performance Metrics

    Publication Year: 2010, Page(s):1 - 4
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (111 KB) | HTML iconHTML

    Rate-based metrics such as floating point operations per second, instructions per cycle and so forth are commonly used to measure computer performance. In addition to the average or mean performance of the metric, indicating the precision of the mean using confidence intervals helps to make informed decisions and comparisons with the data. In this paper, we discuss the determination of confidence ... View full abstract»

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  • A Phase Change Memory as a Secure Main Memory

    Publication Year: 2010, Page(s):5 - 8
    Cited by:  Papers (18)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (93 KB) | HTML iconHTML

    Phase change memory (PCM) technology appears as more scalable than DRAM technology. As PCM exhibits access time slightly longer but in the same range as DRAMs, several recent studies have proposed to use PCMs for designing main memory systems. Unfortunately PCM technology suffers from a limited write endurance; typically each memory cell can be only be written a large but still limited number of t... View full abstract»

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  • Exploiting Internal Parallelism of Flash-based SSDs

    Publication Year: 2010, Page(s):9 - 12
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (161 KB) | HTML iconHTML

    For the last few years, the major driving force behind the rapid performance improvement of SSDs has been the increment of parallel bus channels between a flash controller and flash memory packages inside the solid-state drives (SSDs). However, there are other internal parallelisms inside SSDs yet to be explored. In order to improve performance further by utilizing the parallelism, this paper sugg... View full abstract»

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  • Intra-Socket and Inter-Socket Communication in Multi-core Systems

    Publication Year: 2010, Page(s):13 - 16
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB) | HTML iconHTML

    The increasing computational and communication demands of the scientific and industrial communities require a clear understanding of the performance trade-offs involved in multi-core computing platforms. Such analysis can help application and toolkit developers in designing better, topology aware, communication primitives intended to suit the needs of various high end computing applications. In th... View full abstract»

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  • A Case for Alternative Nested Paging Models for Virtualized Systems

    Publication Year: 2010, Page(s):17 - 20
    Cited by:  Papers (4)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (145 KB) | HTML iconHTML

    Address translation often emerges as a critical performance bottleneck for virtualized systems and has recently been the impetus for hardware paging mechanisms. These mechanisms apply similar translation models for both guest and host address translations. We make an important observation that the model employed to translate from guest physical addresses (GPAs) to host physical addresses (HPAs) is... View full abstract»

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  • Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications

    Publication Year: 2010, Page(s):21 - 24
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB) | HTML iconHTML

    While Moore's law scaling continues to double transistor density every technology generation, supply voltage reduction has essentially stopped, increasing both power density and total energy consumed in conventional microprocessors. Therefore, future processors will require an architecture that can: a) take advantage of the massive amount of transistors that will be available; and b) operate these... View full abstract»

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  • SMT-Directory: Efficient Load-Load Ordering for SMT

    Publication Year: 2010, Page(s):25 - 28
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (122 KB) | HTML iconHTML

    Memory models like SC, TSO, and PC enforce load-load ordering, requiring that loads from any thread appear to occur in program order to all other threads. Out-of-order execution can violate load-load ordering. Multi-processors with out-of-order cores detect load-load ordering violations by snooping an age-ordered load queue on cache invalidations or evictions-events that act as proxies for the com... View full abstract»

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  • A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors

    Publication Year: 2010, Page(s):29 - 32
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (310 KB) | HTML iconHTML

    This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by the large non-uniform distribution of memory accesses across cache sets in different L2 banks. DPAP decouples the physical locations of cache blocks from their addresses for the sake of reducing misses caused by destruc... View full abstract»

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  • Leveraging Unused Cache Block Words to Reduce Power in CMP Interconnect

    Publication Year: 2010, Page(s):33 - 36
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (151 KB) | HTML iconHTML

    Power is of paramount importance in modern computer system design. In particular, the cache interconnect in future CMP designs is projected to consume up to half of the system power for cache fills and spills. Despite the power consumed by spills and fills, a significant percentage of each cache line is unused prior to eviction from the cache. If unused cache block words can be identified, this in... View full abstract»

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  • Information for authors

    Publication Year: 2010, Page(s): c3
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    Freely Available from IEEE
  • IEEE Computer Society [Cover4]

    Publication Year: 2010, Page(s): c4
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Aims & Scope

IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Daniel J. Sorin
Duke University
Electrical & Computer Engineering
PO Box 90291
Durham, NC 27708
e-mail: sorin@ee.duke.edu