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Semiconductor Manufacturing, IEEE Transactions on

Issue 1 • Date Feb 1993

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Displaying Results 1 - 9 of 9
  • Modeling, optimization and control of spatial uniformity in manufacturing processes

    Publication Year: 1993 , Page(s): 41 - 57
    Cited by:  Papers (17)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1384 KB)  

    Spatial uniformity, or the uniformity of product output characteristics at different locations in a batch of product is modeled, optimized, and controlled using a methodology called multiple response surfaces, which may be used to characterize the results of an experimental design. Multiple, low-order polynomial models are used to model the output characteristics at each of several sites within a batch of product. The uniformity model is then obtained by manipulating these multiple models. The approach is compared to the traditional method of fitting a single high-order polynomial to the calculated uniformity. Experimental results confirm that similar or improved modeling accuracy is obtained with fewer data points using the new method due to the use of low-order models. Characteristics of the approach are examined both analytically and in application to plasma etching, silicon epitaxy, tungsten chemical vapor deposition (CVD) and the simulation of polysilicon low-pressure CVD (LPCVD) View full abstract»

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  • Automated malfunction diagnosis of semiconductor fabrication equipment: a plasma etch application

    Publication Year: 1993 , Page(s): 28 - 40
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1100 KB)  

    A general methodology for the automated diagnosis of integrated circuit fabrication equipment is presented. The technique combines the best aspects of quantitative algorithmic diagnosis and qualitative knowledge-based approaches. Evidence from equipment maintenance history, real-time tool data, and incline measurements are integrated using evidential reasoning. This methodology is applied to the identification of faults in the Lam Research Autoetch 490 automated plasma etching system located in the Berkeley Microfabrication Laboratory View full abstract»

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  • Independent control of ion density and ion bombardment energy in a dual RF excitation plasma

    Publication Year: 1993 , Page(s): 58 - 64
    Cited by:  Papers (7)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB)  

    A dual RF excited discharge is described. The dual RF excitation system provides a method to control the substrate self-bias without affecting the state of the discharge. The substrate can be RF-biased utilizing an appropriate excitation frequency and power significantly less than the plasma generating RF power. The substrate self-bias dependence on various system parameters, including substrate excitation frequency, pressure, plasma generating upper electrode RF power, substrate material, and process gas compositions, is described. For a simplified model, a linear relationship between self-bias and RF power is derived using the space-charge limited assumption. The effect of substrate bias on the thermal-oxide etch rate has been studied. The results show good correlation between the ion bombardment energy, i.e., the potential difference across the substrate dark space, and the SiO 2 etch rate. The SiO2 etch rate in a CF4 plasma increases linearly with the ion bombardment energy, having a threshold etch energy of ~19 V View full abstract»

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  • Spin coating over topography

    Publication Year: 1993 , Page(s): 72 - 76
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (676 KB)  

    A model for predicting film thickness profiles around topographical features during spin coating is presented. This model is applicable to features of arbitrary geometry in the two lateral dimensions. This generally permits study of the planarization of real device structures, including both isolated and neighboring features, with any orientation with respect to the wafer center. Predictions from this model agree qualitatively with measured thin-film profiles from interferograms taken during spinning. Phenomena such as pile-up and wakes result from interactions between surface tension and other driving forces in the flow View full abstract»

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  • Automated wafer level QBD measurement for production control

    Publication Year: 1993 , Page(s): 83 - 87
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    A novel technique is presented for the swift measurement of the charge necessary to induce failure in a thin SiO2 film (QBD). This can form part of a powerful wafer-level reliability evaluation program through inclusion within an automated test system. The method is demonstrated by extracting the distribution of QBD values from across several 150-mm wafers View full abstract»

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  • A layout-driven yield predictor and fault generator for VLSI

    Publication Year: 1993 , Page(s): 77 - 82
    Cited by:  Papers (14)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (596 KB)  

    The authors present an efficient approach to probability-graded fault list generation, and critical area calculation for IC yield production. The approach is also efficient to program because it is built on top of existing design rule checking routines. The accuracy of the tool is enhanced by including in the critical area calculations adjustments for defects occurring at the end of a feature and validating shorts before including the associated critical area in the sum. It would be possible to make the approach more efficient by going to an entirely graph-based approach, thus avoiding the physical tile generation step View full abstract»

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  • In situ measurement of wafer temperatures in a low pressure chemical vapor deposition furnace

    Publication Year: 1993 , Page(s): 65 - 71
    Cited by:  Papers (6)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (640 KB)  

    Axial and radial temperature profiles within the wafer load of a multiwafer LPCVD furnace were measured in situ using a pair of instrumented wafers. The measurements confirm that the wafer load is not in thermal equilibrium with the furnace tube, as has been widely assumed in many modeling studies. The measurements confirm temperature variations predicted previously from a study of polysilicon film thickness profiles. Temperature variations were small for wafers near the center of the 150-wafer load. However, axial variations of up to 25°C and radial variations of up to 5°C were measured at the extremes of the wafer load. For a representative polysilicon deposition data set, axial and radial thin-film thickness variations were found to correlate closely with measured temperature variations. The temperature profile was found to be insensitive to gas composition and flowrate, establishing radiation as the dominant mode of heat transfer. A pair of polysilicon coated quartz radiation shields was shown to improve polysilicon film thickness uniformity both down the load (along the furnace axis) and across each wafer View full abstract»

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  • Advanced `contact engineering' for submicron VLSI multilevel metallization

    Publication Year: 1993 , Page(s): 22 - 27
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB)  

    Two contact engineering methods developed for submicron contact openings are described. The two methods, SCOPE (simultaneous contact and planarization etch) and PACE (planarization after contact etch), interchange the process sequences of dielectric planarization and contact etch to achieve uniform contact etch. Both etching processes eliminate the need for oxide reflow thereby minimizing the thermal budget after source/drain formation. Since the dielectric is planarized either during the contact etch (e.g., with SCOPE) or after contact etch (e.g., with PACE), the need for extensive overetching of the oxide due to the dissimilar contact depths is also eliminated. As a result, contact resistance and leakage currents are significantly reduced in comparison to results obtained with dielectrics planarized before etching. In addition, etching of field oxide due to pattern misalignment is minimized since the contacts are of similar depth View full abstract»

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  • Systematic design of phase-shifting masks with extended depth of focus and/or shifted focus plane

    Publication Year: 1993 , Page(s): 1 - 21
    Cited by:  Papers (3)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2280 KB)  

    An optimization based algorithm for designing phase-shifting masks is proposed. The approach is an extension of the previous work in the sense that the intensity image is optimized at a number of optical planes rather than just the focus plane. In addition, the algorithm can be used to design masks with shifted focus plane and/or extended depth of focus. The concept of a dual mask is introduced, and its consequences for practical phase-shifting mask design are shown. The proposed design techniques are applied to single line phase connectors, cross phase connectors, contact holes and bright lines. Simulation and experimental results verify the capability of the design technique for extending depth of focus and shift the focus plane View full abstract»

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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721