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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 6 • Date June 2010

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2010, Page(s):C1 - C4
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2010, Page(s): C2
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  • Guest Editorial: Special Section on the ACM/IEEE Symposium on Networks-on-Chip 2009

    Publication Year: 2010, Page(s):853 - 854
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  • Virtual Point-to-Point Connections for NoCs

    Publication Year: 2010, Page(s):855 - 868
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3432 KB) | HTML iconHTML

    In this paper, we aim to improve the performance and power metrics of packet-switched network-on-chips (NoCs) and benefits from the scalability and resource utilization advantages of NoCs and superior communication performance of point-to-point dedicated links. The proposed method sets up the virtual point-to-point (VIP) connections over one virtual channel (which bypasses the entire router pipeli... View full abstract»

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  • The Connection-Then-Credit Flow Control Protocol for Heterogeneous Multicore Systems-on-Chip

    Publication Year: 2010, Page(s):869 - 882
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5902 KB) | HTML iconHTML

    Connection-then-credits (CTC) is a novel end-to-end flow control protocol to handle message-dependent deadlocks in best-effort networks-on-chip (NoC) for embedded multicore systems-on-chip (SoCs). CTC is based on the classic end-to-end credit-based flow control protocol but differs from it because it uses a network interface microarchitecture where a single credit counter and a single input data q... View full abstract»

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  • Fault Tolerant Network on Chip Switching With Graceful Performance Degradation

    Publication Year: 2010, Page(s):883 - 896
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6565 KB) | HTML iconHTML

    The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity even if network components are out of service due to faults, which will appear at an increasing rate with future chip technology nodes. This paper is based on a new, fine-grained functional fault model and a corresponding d... View full abstract»

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  • A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms

    Publication Year: 2010, Page(s):897 - 910
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6434 KB) | HTML iconHTML

    This paper presents a globally-asynchronous locally-synchronous (GALS)-compatible circuit-switched on-chip network that is well suited for use in many-core platforms targeting streaming digital signal processing and embedded applications which typically have a high degree of task-level parallelism among computational kernels. Inter-processor communication is achieved through a simple yet effective... View full abstract»

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  • Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems

    Publication Year: 2010, Page(s):911 - 924
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1593 KB) | HTML iconHTML

    To exploit the power of modern heterogeneous multiprocessor embedded platforms on partitioned applications, the designer usually needs to efficiently map and schedule all the tasks and the communications of the application, respecting the constraints imposed by the target architecture. Since the problem is heavily constrained, common methods used to explore such design space usually fail, obtainin... View full abstract»

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  • SPARE—A Scalable Algorithm for Passive, Structure Preserving, Parameter-Aware Model Order Reduction

    Publication Year: 2010, Page(s):925 - 938
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6607 KB) | HTML iconHTML

    This paper describes a flexible and efficient new algorithm for model order reduction of parameterized systems. The method is based on the reformulation of the parameterized system as a perturbation-like parallel interconnection of the nominal transfer function and the nonparameterized transfer function sensitivities with respect to the parameter variations. Such a formulation reveals an explicit ... View full abstract»

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  • Layout Decomposition Approaches for Double Patterning Lithography

    Publication Year: 2010, Page(s):939 - 952
    Cited by:  Papers (22)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4896 KB) | HTML iconHTML

    In double patterning lithography (DPL) layout decomposition for 45 nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing. However, there exist pattern configurations for which pattern features separated by less than the minimum coloring spacing cannot be assigned different c... View full abstract»

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  • An Adaptive Flash Translation Layer for High-Performance Storage Systems

    Publication Year: 2010, Page(s):953 - 965
    Cited by:  Papers (5)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4993 KB) | HTML iconHTML

    While the capacity of flash-memory storage systems keeps increasing significantly, an effective and efficient management of flash-memory space has become a critical design issue. Different granularities in space management impose different management costs and mapping efficiency. In this paper, we will explore an address translation mechanism (AddrTM) that can dynamically and adaptively switch bet... View full abstract»

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  • A Novel Test Application Scheme for High Transition Fault Coverage and Low Test Cost

    Publication Year: 2010, Page(s):966 - 976
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3309 KB) | HTML iconHTML

    This paper presents a new method for improving transition fault coverage in hybrid scan testing. It is based on a novel test application scheme, in order to break the functional dependence of broadside testing. The new technique analyzes the automatic test pattern generation conflicts in broadside test generation and skewed-load test generation, and tries to control the flip-flops with the most in... View full abstract»

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  • Diagnosis of Integrated Circuits With Multiple Defects of Arbitrary Characteristics

    Publication Year: 2010, Page(s):977 - 987
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6222 KB) | HTML iconHTML

    This paper describes a multiple-defect diagnosis methodology that is flexible in handling various defect behaviors and arbitrary failing pattern characteristics. Unlike some other approaches, the search space of the diagnosis method does not grow exponentially with the number of defects. Results from extensive simulation experiments and real failing integrated circuits show that this method can ef... View full abstract»

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  • IR-Drop Management in FPGAs

    Publication Year: 2010, Page(s):988 - 993
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2371 KB) | HTML iconHTML

    This paper presents novel computer-aided design (CAD) techniques for mitigating IR-drops in field-programmable gate arrays (FPGAs). The proposed placement and routing relies on reducing the switching activities in local regions in the FPGA fabric to improve the profile of the supply voltage distribution. The proposed techniques reduce IR-drops and the variance of the supply voltage distribution ac... View full abstract»

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  • Modeling Interrupts for Software-Based System-on-Chip Verification

    Publication Year: 2010, Page(s):993 - 997
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3039 KB) | HTML iconHTML

    The interrupt mechanism in a system-on-chip (SoC) joins the SoCs hardware and software behaviors. We model interrupts as logical rather than physical events and accordingly provides guidelines to compose software components including interrupt-service-routines. As a benefit, classical indeterministic behaviors (due to the parallelism) in the software domain, such as preemption and nesting, can be ... View full abstract»

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  • 17th IEEE International Conference on Electronics Circuits and Systems(ICECS 2010)

    Publication Year: 2010, Page(s): 998
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2010, Page(s): 999
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  • Introducing ieee.tv [advertisement]

    Publication Year: 2010, Page(s): 1000
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2010, Page(s): C3
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu