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Electron Devices, IEEE Transactions on

Issue 6 • Date June 2010

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Displaying Results 1 - 25 of 44
  • Table of contents

    Page(s): C1 - C4
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  • IEEE Transactions on Electron Devices publication information

    Page(s): C2
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  • Changes in the Editorial Board

    Page(s): 1193
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  • Change in Submission Procedure

    Page(s): 1194
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  • A Study on Pre-Oxidation Nitrogen Implantation for the Improvement of Channel Mobility in 4H-SiC MOSFETs

    Page(s): 1195 - 1200
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (545 KB) |  | HTML iconHTML  

    Detailed investigations on the pre-oxidation nitrogen implantation process for the improvement of channel mobility in 4H-SiC MOSFETs are reported. Comparisons with conventional thermally nitrided gate oxides are highlighted. The results of a nitrogen dose dependence study indicate that higher N implantation doses lead to higher peak field-effect mobilities but lower threshold voltages. This apparently correlates with the interface trap density near the conduction band of 4H-SiC, as previous work suggests, but an alternate mechanism associated with counter doping of the MOSFET p-well via N implantation is proposed here. Analysis of the experimental results suggests that the counter-doping mechanism is more likely to be the dominant effect. View full abstract»

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  • On the Partial Filling of the Intermediate Band in IB Solar Cells

    Page(s): 1201 - 1207
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    Based on a generalized model of the Shockley-Read-Hall (SRH) statistics published elsewhere, the effect of the partial filling of the intermediate band (IB) in IB solar cells and the ways of producing it are analyzed, as is its influence on the electron-hole pair generation by subband-gap photons. The differences between cells with the conduction band and the IB thermally coupled and uncoupled are stressed. This paper is oriented toward the explanation of the operation of quantum-dot solar cells, where the IB is formed from electron-confined states but can also be applicable to other IB systems. View full abstract»

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  • AlGaN/GaN/AlGaN DH-HEMTs Breakdown Voltage Enhancement Using Multiple Grating Field Plates (MGFPs)

    Page(s): 1208 - 1216
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1619 KB) |  | HTML iconHTML  

    GaN-based high-electron mobility transistors with planar multiple grating field plates (MGFPs) for high-voltage operation are described. A synergy effect with additional electron channel confinement by using a heterojunction AlGaN back barrier (BB) is demonstrated. Suppression of the OFF-state subthreshold gate and drain leakage currents enables breakdown voltage enhancement over 700 V and a low ON-state resistance of 0.68 mΩ × cm2. Such devices have a minor tradeoff in ON-state resistance, lag factor, maximum oscillation frequency, and cutoff frequency. A systematic study of the MGFP design and the effect of Al composition in the BB is described. Physics-based device simulation results give insight into electric field distribution and charge carrier concentration, depending on the field plate design. View full abstract»

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  • The Effect of the Vertical Load Distribution on the Luminance of a Plasma Display Panel

    Page(s): 1217 - 1223
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    In a plasma display panel, the displayed luminance is affected by the vertical load distribution when the X electrodes of all scan lines are connected to the X driver through a common X electrode. In this brief, the effect of the vertical distance between the target cell and the load on the luminance variation is formulated as a load weight. The effect of the load distribution of a complete panel is then formulated as the effective total load, which enables an accurate prediction of the variation in the luminance as affected by the vertical load distribution. The mean absolute error is improved by 75.43% by the proposed method compared with an earlier previous method that does not take the vertical load distribution into consideration. View full abstract»

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  • Array of Two UV-Wavelength Detector Types

    Page(s): 1224 - 1229
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1106 KB) |  | HTML iconHTML  

    An approach to fabricate a set of simultaneously operating dual-UV-wavelength detectors is described. The fabrication flow relies on the confined-epitaxy growth method. The confined epitaxial AlxGa1-xN-layer stacking approach is used to establish simultaneous multiple UV-wavelength detection. The chosen stoichiometries of specific epitaxial layers set the wavelength sensitivity at approximately 355 nm for pixel A and 320 nm for pixel B. Spectral responsivity plots of the detectors clearly show the dual-UV-color sensitivity of the pair. The detectors have signal-to-noise ratios of 15 and 17 and spectral responsivity values of 0.12 AAV and 0.05 AAV for pixel A and pixel B, respectively. View full abstract»

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  • Analysis of Dark Current Mechanisms for Split-Off Band Infrared Detectors at High Temperatures

    Page(s): 1230 - 1236
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB) |  | HTML iconHTML  

    An analysis of dark current mechanisms has been performed on high-operating-temperature (up to 330 K) split-off (SO) band p+-GaAs/AlGaAs heterojunction infrared detectors (3-5 μm). In contrast to conventional 1-D current models due to carrier transport based on tunneling and/or thermionic emission mechanisms, a 2-D electrical model is used to explain nonuniformity degradation of zero-bias differential resistance (RoA) with temperatures as measured on SO detectors. The 2-D characteristic of carrier transport could have the limitation on high-temperature performances of detectors and, hence, needs optimizing. A theoretical model shows that this 2-D effect can be reduced by structural modifications such as using smaller mesa sizes, higher doping of the p+ -GaAs layer, and a higher potential barrier that prospectively provides better electrical uniformity for SO detectors working at high temperatures. View full abstract»

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  • Single-Layer InAs Quantum Dots for High-Performance Planar Photodetectors Near 1.3 \mu\hbox {m}

    Page(s): 1237 - 1242
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (483 KB) |  | HTML iconHTML  

    The potential of InAs quantum-dot (QD) photodetectors for room-temperature high-speed operation at wavelengths near 1.3 μm is evaluated. Specifically, planar metal-semiconductor-metal structures on GaAs substrates containing one absorption layer of self-assembled InAs QDs embedded in Ga(In)As matrices are fabricated, characterized, and analyzed. Light absorption, optically generated carrier transport, and collection mechanisms are studied. The role of the QD embedding matrix in the lateral transport of the photogenerated carriers is also studied by comparing structures with QDs in GaAs and In0.15Ga0.85As matrices. Devices show low dark currents in tens of nanoamperes and high light sensitivity when adjusted to QD volumes, whereas external quantum efficiency remains in the range 10-5-10-4 for all fabricated samples. The time response of the fabricated devices is obtained using an excitation wavelength resonant with QD interband transitions, thus allowing the photogeneration of electron-hole pairs inside the dots. Results prove detection capability of a single layer of QDs in a common photodetector structure with a full-width half-maximum time response on the order of 10 ps. A long tail, about 100 ps, but at a small fraction of the peak response amplitude, is also observed, suggesting mechanisms for charge transport and collection. View full abstract»

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  • Strained-Silicon Heterojunction Bipolar Transistor

    Page(s): 1243 - 1252
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    Experimental and modeling results are reported for high-performance strained-silicon heterojunction bipolar transistors (HBTs), comprising a tensile strained-Si emitter and a compressively strained Si0.7Ge0.3 base on top of a relaxed Si0.85Ge0.15 collector. By using a Si0.85Ge0.15 virtual substrate strain platform, it is possible to utilize a greater difference in energy band gaps between the base and the emitter without strain relaxation of the base layer. This leads to much higher gain, which can be traded off against lower base resistance. There is an improvement in the current gain β of 27 × over a conventional silicon bipolar transistor and 11× over a conventional SiGe HBT, which were processed as reference devices. The gain improvement is largely attributed to the difference in energy band gap between the emitter and the base, but the conduction band offset between the base and the collector is also important for the collector current level. View full abstract»

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  • Investigation of Back-Bias Capacitance Coupling Coefficient Measurement Methodology for Floating-Gate Nonvolatile Memory Cells

    Page(s): 1253 - 1260
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (316 KB) |  | HTML iconHTML  

    In this paper, we give a thorough investigation of a new capacitance coupling coefficient measurement methodology (a back-bias method) that extracts the gate capacitance coefficient of floating-gate memory cells. This measurement methodology that utilizes simple current-voltage measurements presents several advantages over current methodologies. It includes a figure of merit for determining the matching performance of a reference transistor to a memory cell, which plays a crucial role for the extraction of the correct gate coupling coefficient value. By this means, we investigate, for the first time, the impact of structural differences between a reference transistor and a memory cell on the gate coupling coefficient extraction. The back-bias method is compared with commonly used gate coupling coefficient extraction methods, and it is shown that it has a smaller extraction error for nonmatching reference transistors and memory cell pairs. Furthermore, it is demonstrated how the gate coupling coefficient extraction can be corrected if matching reference and memory cell structures cannot be found. View full abstract»

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  • Fabrication and Characterization of Through-Substrate Interconnects

    Page(s): 1261 - 1268
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (945 KB) |  | HTML iconHTML  

    We developed a through-substrate copper-damascene interconnect technology in silicon with minimal impedance. Via impedance was extracted using parameter measurements at 50 GHz that were matched to simple circuit models. The extracted impedance shows resistances ≤ 1 Ω, record-low inductance for aspect ratios > 4, and sidewall capacitance that approaches the theoretical value. For an aspect ratio of 10 (10 in diameter and 100 high), the through-substrate via has an average inductance of 36 pH at 10 GHz, resistance of 0.6 at 1 GHz, and sidewall capacitance of 0.3 pF. View full abstract»

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  • High Effective Gummel Number of CVD Boron Layers in Ultrashallow \hbox {p}^{+}\hbox {n} Diode Configurations

    Page(s): 1269 - 1278
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    Deposited boron layers fabricated by exposing silicon to diborane (B2H6) gas in an atmospheric-pressure chemical vapor deposition reactor are investigated with respect to their electrical properties. At the applied temperatures from 500°C to 700°C, the deposition forms a nanometer-thick layer stack of amorphous boron (α-B) and boron-silicon compound (BxSiy), whereas the crystalline Si substrate is p-doped to depths below 10 nm, depending on the temperature and exposure time. The as-deposited layers can be used to fabricate high-quality p+n diodes with low series resistance and low saturation current values that are comparable with those of conventional deep p+ junctions. By investigating p-n-p structures with p+ B-deposited emitters, it is shown that the presence of the α-B layer increases the effective Gummel number of the diffused emitter up to about a factor of 60. The α-B layer is also demonstrated to be a stable and controllable supply of B for the formation of deep p-type regions by thermal drive-in. View full abstract»

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  • Contact Resistance Reduction Technology Using Aluminum Implant and Segregation for Strained p-FinFETs With Silicon–Germanium Source/Drain

    Page(s): 1279 - 1286
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (938 KB) |  | HTML iconHTML  

    We have demonstrated the introduction of an additional aluminum (Al) implant step in the fabrication of strained p-FinFETs with silicon-germanium (SiGe) source/drain (S/D). Al is implanted. into the p+-SiGe S/D region at energy of 10 keV and a dose of 2 × 1014 atoms/cm2, followed by its segregation at the NiSiGe/p+-SiGe S/D interface during germanosilicidation. The presence of Al at this interface leads to lowering of the effective Schottky barrier height for hole conduction, which, in essence, lowers the S/D contact resistance RC · RC is a dominant component of the FinFET parasitic series resistance RSD, which is lowered by approximately 25% using this technology, correspondingly leading to a substantial increase in the saturation drive current. The novel Al-segregated NiSiGe/p+-SiGe S/D contact junction in p-FinFETs does not degrade short-channel effects or the NiSiGe film morphology. View full abstract»

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  • A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performance

    Page(s): 1287 - 1294
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    For the first time, we propose a novel bottom spacer fin-shaped field-effect-transistor (FinFET) structure for logic applications suitable for system-on-chip (SoC) requirements. The proposed device achieved improved short-channel, power-delay, and self-heating performance compared with standard silicon-on-insulator FinFETs. Process aspects of the proposed device are also discussed in this paper. Physical insight into the improvement toward the short-channel performance and power dissipation is given through a detailed 3-D device/mixed-mode simulation. The self-heating behavior of the proposed device is compared with standard FinFETs by using detailed electrothermal simulations. The proposed device requires an extra process step but enables smaller electrical width for self-loaded circuits and is an excellent option for SoC applications. View full abstract»

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  • Mobility and Velocity Enhancement Effects of High Uniaxial Stress on Si (100) and (110) Substrates for Short-Channel pFETs

    Page(s): 1295 - 1300
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (575 KB) |  | HTML iconHTML  

    An experimental study of mobility and velocity enhancement effects is reported for highly strained short-channel p-channel field-effect transistors (pFETs) using a damascene-gate process on Si (100) and (110) substrates. The relationship between the mobility and the saturation velocity of hole under a compressive stress over 2.0 GPa is discussed. The local channel stress of 2.4 GPa is successfully measured with ultraviolet-Raman spectroscopy for the 30-nm-gate-length device with top-cut compressive-stress SiN liner and embedded SiGe. Mobility and saturation-velocity enhancements of (100) substrate are larger than those of (110) under the high channel stress. In consequence, the saturation current on (100) is larger than that on (110) for the pFETs with higher channel stress and shorter gate length. Moreover, the large enhancement rate of saturation velocity to mobility by the uniaxial stress suggests high injection velocity for the pFETs with the stressors since the high channel stress is induced near the potential peak of the source by using the damascene-gate technology. View full abstract»

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  • Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node

    Page(s): 1301 - 1309
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1637 KB) |  | HTML iconHTML  

    The performance and threshold voltage variability of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are compared against those of conventional bulk MOSFETs via 3-D device simulation with atomistic doping profiles. Compact (analytical) modeling is then used to estimate six-transistor SRAM cell performance metrics (i.e., read and write margins, and read current) at the 22 nm CMOS technology node. The dependences of these metrics on cell ratio, pull-up ratio, and operating voltage are analyzed for FD-SOI versus bulk SRAM cells. Iso-area and iso-yield comparisons are then made to determine the yield and cell-area benefits of FD-SOI technology, respectively. Finally, the minimum operating voltages required for FD-SOI and bulk SRAM cells to meet the six-sigma yield requirement are compared. View full abstract»

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  • Statistical Evaluation of Process Damage Using an Arrayed Test Pattern in a Large Number of MOSFETs

    Page(s): 1310 - 1318
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1380 KB) |  | HTML iconHTML  

    Evaluating the statistical variations of MOSFETs is important for realizing accurate analog circuits and large-scale-integration devices. A new evaluation method for the statistical variation of the electrical characteristics of MOSFETs is presented. We have developed a test circuit for understanding the statistical and local variations of MOSFETs in a very short time. We demonstrate that the electrical characteristics in more than one million MOSFETs, such as the threshold voltage and the subthreshold swing (S-Factor), are measured in 30 min and that the measured results are very efficient in developing the fabrication process, the process equipment, and the device structure to reduce the statistical and local characteristic variation. View full abstract»

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  • LDD and Back-Gate Engineering for Fully Depleted Planar SOI Transistors with Thin Buried Oxide

    Page(s): 1319 - 1326
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    We investigate planar fully depleted silicon-on-insulator(SOI) MOSFETs with a thin buried oxide (BOX) and a ground plane (GP). To study the depletion effects in the lightly doped drain (LDD) and substrate, we compare different BOX/GP/ LDD structure combinations. A novel GP back-gate engineering approach is introduced to improve both short-channel effects (SCEs) and LDD resistance. In this technique, an LDD/channel/ LDD mirror doping structure is reproduced in the back gate underneath the thin BOX. It is shown that SCEs are rather insensitive to SOI layer thickness variations and remain well controlled for gate lengths down to 15 nm for both nMOS and pMOS transistors due to outstanding electrostatic control: 63 mV/dec subthreshold swing and 7 mV/V drain-induced barrier lowering at Vdd = 1 V. The shift of the threshold voltage ΔVth with silicon film thickness Tsi down to 0.5 mV/nm is obtained. Simulations show that a 20% reduction in LDD resistance can be achieved in thin BOX devices with an optimized GP, as compared with thick BOX transistors. In addition, an improvement in drive current is also reported. View full abstract»

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  • Why the Universal Mobility Is Not

    Page(s): 1327 - 1333
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (717 KB) |  | HTML iconHTML  

    Examples taken from ultrathin silicon-on-insulator (SOI) transistors tend to contradict the universality of mobility-field dependence. We revisit the meaning of the effective field concept and its implications on the universal mobility curve (UMC). Poisson-Schroedinger simulations point out the inappropriateness of the standard definitions of effective field when dealing with SOI or double-gate devices. Different carrier distributions can lead to the same value of the effective field breaking the foundation of the universality. The presence of two different gate stacks, the coexistence and coupling of two channels, and the spreading of carriers in the body are interesting nonlocal effects that are not accounted for by the UMC. Selected practical results showing the UMC failure in SOI metal-oxide-semiconductor field-effect transistors are presented. The actual behavior of the effective mobility is illustrated, shedding light on the limitations of the universal mobility/effective field representation. View full abstract»

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  • Compact and Distributed Modeling of Cryogenic Bulk MOSFET Operation

    Page(s): 1334 - 1342
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    We have developed compact and physics-based distributed numerical models for cryogenic bulk MOSFET operation down to 20 K to advance simulation and first-pass design of device and circuit operation at low temperatures. To achieve this, we measured and simulated temperature-dependent current-voltage characteristics of 0.16- and 0.18- bulk MOSFETs. Our measurements indicate that these MOSFETs supply approximately 40% more current in the saturation and linear regions of operation when they are cooled from room temperature to 20 K. The threshold voltage monotonically increases as the temperature is lowered, but it saturates below 40 K. The subthreshold slope decreases with the temperature lowering but at a rate that is less than theoretically predicted. The extrapolation of the subthreshold slope indicates a finite value at near absolute zero. We show that the measured behavior can be well corroborated with distributed numerical simulations using the drift-diffusion transport model. In addition, to obtain a compact model for use in low-temperature circuit design, SPICE-type compact models need to be modified to incorporate the subtle temperature effects that are not part of the standard models. To this end, we use the analog behavioral language Verilog-A and the BSIM3 model equation set to include additional temperature dependences into the standard compact models to accurately reproduce measured characteristics. View full abstract»

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  • Understanding Strain-Induced Drive-Current Enhancement in Strained-Silicon n-MOSFET and p-MOSFET

    Page(s): 1343 - 1354
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1208 KB) |  | HTML iconHTML  

    Strain greatly affects the electrical properties of silicon because strain changes the energy band structure of silicon. In MOSFET devices, the terminal voltages induce electrical fields, which themselves modulate the electronic band structure and interact with strain-induced changes. Applied electrical fields are used to experimentally study different state-of-the-art local and global strain techniques and reveal the different responses of n- and p-MOSFETs to the different strain techniques. It is shown that p-MOSFETs have more low-lateral-field linear drive-current enhancement and less high-lateral-field saturation drive-current enhancement at both low and high vertical fields. The situation is similar for n-MOSFETs at low vertical fields. However, at high vertical fields, n-MOSFET low-lateral-field linear drive-current enhancement is less than the high-lateral-field saturation drive-current enhancement. The origin for this behavior can be found in the different strain effects on the electronic band structure, which results in effective mass reduction and/or scattering suppression. These, in turn, contribute differently to linear and saturation drive-current enhancements in n- and p-MOSFETs. View full abstract»

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  • Effect of Finger Pitch on the Driving Ability of a 40-nm MOSFET With Contact Etch Stop Layer Strain in Multifinger Gated Structure

    Page(s): 1355 - 1361
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    Effects of the poly gate finger pitch on, hot-carrier-nduced reliability degradation, and radio frequency characteristics of the 40-nm n-channel metal-oxide-semiconductor field-effect transistors with contact-etch-stop-layer (CESL) strain and multifinger gate structures were systematically investigated by both experiment and technology computer-aided design simulation. The finger pitch influences both the transfer of CESL-induced stress into a channel and the shadow effect of a poly gate on a pocket implantation. The results showed that the effects of the poly gate finger pitch were more obvious for pitches less than 0.12 . Additionally, the change in stress on the channel was dominant for pitches larger than 0.12 , but for pitches less than 0.12 , the modulation of pocket implantation shadow effects became the main controlling factor. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology