IEEE Design & Test of Computers

Issue 3 • May-June 2010

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  • [Front cover]

    Publication Year: 2010, Page(s): c1
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  • Front Covers 
  • Table of Contents

    Publication Year: 2010, Page(s): c2
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  • Toc 
  • Departments [Table of Contents]

    Publication Year: 2010, Page(s): 1
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  • Enabling design and manufacturing through innovations in DFT

    Publication Year: 2010, Page(s): 2
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  • [Masthead]

    Publication Year: 2010, Page(s): 3
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  • Microprocessor Software-Based Self-Testing

    Publication Year: 2010, Page(s):4 - 19
    Cited by:  Papers (100)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1146 KB) | HTML iconHTML

    This article discusses the potential role of software-based self-testing in the microprocessor test and validation process, as well as its supplementary role in other classic functional- and structural-test methods. In addition, the article proposes a taxonomy for different SBST methodologies according to their test program development philosophy, and summarizes research approaches based on SBST t... View full abstract»

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  • Economic Analysis of the HOY Wireless Test Methodology

    Publication Year: 2010, Page(s):20 - 30
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (949 KB) | HTML iconHTML

    The HOY (Hypothesis, Odyssey, and Yield) test system provides wireless test access and embedded DFT, while offering lower cost and better performance than conventional ATE. This article briefly describes HOY, then proposes a test cost model to compare it with conventional ATE, and analyzes the test cost of these two methods for different manufacturing processes, area overheads, die sizes, manufact... View full abstract»

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  • Automatic Test Wrapper Synthesis for a Wireless ATE Platform

    Publication Year: 2010, Page(s):31 - 41
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1092 KB) | HTML iconHTML

    To ensure reliable test data communication in a wireless test system, information can be encapsulated in packets equipped with error correction and retransmission capability. Systems employing such an approach require a complex test interface (test wrapper) to bridge communication and test modules. This article proposes a modular test wrapper design and an automation tool to create a wrapper for a... View full abstract»

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  • Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch

    Publication Year: 2010, Page(s):42 - 53
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1351 KB) | HTML iconHTML

    For sub-65-nm design, many timing effects, if not explicitly and accurately modeled and simulated, can result in an unexpected timing mismatch between simulated and observed timing behavior on silicon chips. We describe a feature-ranking methodology to analyze and rank potential design-related issues, explaining how diverse features can be used to encode the potential design issues and how feature... View full abstract»

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  • Determination of Dominant-Yield-Loss Mechanism with Volume Diagnosis

    Publication Year: 2010, Page(s):54 - 61
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB) | HTML iconHTML

    The cost and cycle time for determining the root cause of yield loss continues to increase as semiconductor technology scales down. A new technique, Axiom, helps yield and product engineers determine the root cause of loss directly from diagnosis results. Consequently, root-cause cycle time is dramatically reduced, resulting in a higher physical-failure analysis success rate and reduced costs. View full abstract»

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  • NSF Workshop on EDA: Past, Present, and Future (Part 2)

    Publication Year: 2010, Page(s):62 - 74
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (439 KB) | HTML iconHTML

    The July 2009 National Science Foundation workshop on EDA had two objectives: First, to reflect on EDA's success and to see if EDA practices can influence other fields of computer science and if EDA methodology can be applied to other application domains; and second, to review the progress made under the National Design Initiative and evaluate what new directions and topics should be added to the ... View full abstract»

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  • Conference Reports

    Publication Year: 2010, Page(s): 75
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  • Design Automation Technical Committee Newsletter

    Publication Year: 2010, Page(s):76 - 77
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  • Concurrent checking for logic [review of "New Methods of Concurrent Checking (Goessel, M., et al; 2008)]

    Publication Year: 2010, Page(s):80 - 81
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  • Scaling: More than Moore's law

    Publication Year: 2010, Page(s):86 - 87
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (123 KB) | HTML iconHTML

    Discerning "the road ahead" is more difficult than ever. For IC design and test, the road ahead has long involved various corollaries of the 50+-year scaling phenomenon known as Moore's law. This column examines the ITRS definitions associated with "More than Moore", along with their implications. View full abstract»

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  • Test Technology TC Newsletter

    Publication Year: 2010, Page(s):78 - 79
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  • CEDA Currents

    Publication Year: 2010, Page(s):82 - 85
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  • Time to retire our benchmarks

    Publication Year: 2010, Page(s): 88
    Cited by:  Papers (1)
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  • [Advertisement - Back cover]

    Publication Year: 2010, Page(s): c3
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  • [Advertisement - Back cover]

    Publication Year: 2010, Page(s): c4
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty