# IEEE Transactions on Semiconductor Manufacturing

## Filter Results

Displaying Results 1 - 25 of 26

Publication Year: 2010, Page(s):C1 - C4
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• ### IEEE Transactions on Semiconductor Manufacturing publication information

Publication Year: 2010, Page(s): C2
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• ### Introduction to the Special Section on Advanced Process Control

Publication Year: 2010, Page(s):149 - 150
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• ### Model Regularization for High-Mix Control

Publication Year: 2010, Page(s):151 - 158
Cited by:  Papers (5)
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Past solutions to the multicontext run-to-run control problem are examined, especially in how they attempt to resolve ill-posedness of the model that leads to a lack of observability. The specific models examined in this paper are assumed to contain a combination of terms, each partitioned by a different context. It is shown that none of the past approaches adequately addresses the observability i... View full abstract»

• ### Properties of EWMA Controllers With Gain Adaptation

Publication Year: 2010, Page(s):159 - 167
Cited by:  Papers (5)
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Exponentially weighted moving average (EWMA) controllers are the most commonly used run-to-run controllers in the semiconductor industry. Using a linear model, an EWMA controller can be implemented in two different ways: either process gain or process intercept can be updated using EWMA statistics at each run. The most commonly used EWMA controller formulation is to keep the process gain as its of... View full abstract»

• ### Compensating for the Initialization and Sampling of EWMA Run-to-Run Controlled Processes

Publication Year: 2010, Page(s):168 - 177
Cited by:  Papers (3)
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The exponentially weighted moving average (EWMA) filter is commonly used for state estimation of run-to-run controllers in semiconductor manufacturing. It is widely known that, when at steady state, the EWMA filter provides the minimum mean square error (MSE) forecast for an integrated moving average (IMA) process. The forecast, however, is optimal if and only if every output of the IMA process is... View full abstract»

• ### Optimization Solvers in Run-to-Run Control

Publication Year: 2010, Page(s):178 - 184
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Semiconductor manufacturing processes with multiple settings or multiple targets, such as furnace applications or processes controlling uniformity, may not have a single algebraic solution, in which case optimization methods are required. While there are many optimization algorithms available, most are not guaranteed to find the global optimum, take longer than an analytic solution, and produce a ... View full abstract»

• ### Addressing Dynamic Process Changes in High Volume Plasma Etch Manufacturing by Using Multivariate Process Control

Publication Year: 2010, Page(s):185 - 193
Cited by:  Papers (4)
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Multivariate plasma etch modeling and control methodology are presented based on 65 and 45 nm gate production data utilizing wafer-to-wafer tool-level scatterometry. The selection of etch recipe variables for optimal control of wafer-to-wafer profile, within-wafer CD, and chamber-to-chamber CD is demonstrated and validated based on wafer-to-wafer, within wafer, and chamber matching experiments. View full abstract»

• ### Large-Scale Semiconductor Process Fault Detection Using a Fast Pattern Recognition-Based Method

Publication Year: 2010, Page(s):194 - 200
Cited by:  Papers (30)
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Fault detection and classification (FDC) has been recognized as an integral component of the advanced process control (APC) framework in the semiconductor industry, as it helps to improve overall equipment efficiency (OEE). However, some unique characteristics of semiconductor manufacturing processes have posed challenges for FDC applications, such as nonlinearity in most batch processes, and mult... View full abstract»

• ### Introducing a Unified PCA Algorithm for Model Size Reduction

Publication Year: 2010, Page(s):201 - 209
Cited by:  Papers (21)
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Principal component analysis (PCA) is a technique commonly used for fault detection and classification (FDC) in highly automated manufacturing. Because PCA model building and adaptation rely on eigenvalue decomposition of parameter covariance matrices, the computational effort scales cubically with the number of input variables. As PCA-based FDC applications monitor systems with more variables, or... View full abstract»

• ### Scheduling Back-End Operations in Semiconductor Manufacturing

Publication Year: 2010, Page(s):210 - 220
Cited by:  Papers (13)
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The importance of back-end operations in semiconductor manufacturing has been growing steadily in the face of higher customer expectations and stronger competition in the industry. In order to achieve low cycle times, high throughput and high utilization while improving due-date performance, more effective tools are needed to support machine setup and lot dispatching decisions. This paper presents... View full abstract»

• ### Yield Management Enhanced Advanced Process Control System (YMeAPC)—Part I: Description and Case Study of Feedback for Optimized Multiprocess Control

Publication Year: 2010, Page(s):221 - 235
Cited by:  Papers (13)  |  Patents (4)
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In today's competitive semiconductor manufacturing environment, improving fab productivity and reducing cost requires that all systems work collaboratively towards production, quality and cost targets. Equipment engineering systems (EES), including advanced process control have risen to the top as key enablers for maximizing fab productivity, however these systems have been hindered as they focus ... View full abstract»

• ### Forward Echelon-Based Inventory Monitoring in a Semiconductor Supply Chain

Publication Year: 2010, Page(s):236 - 245
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As the semiconductor industry faces fierce competition, it is essential for the semiconductor supply chain to integrate the front end and the back end to provide better service to customers. However, each member of the supply chain has different levels of power and pursues different goals which results in poor performance and difficulty monitoring it. In order to enhance service levels and to impr... View full abstract»

• ### Scheduling Wafer Lots on Diffusion Machines in a Semiconductor Wafer Fabrication Facility

Publication Year: 2010, Page(s):246 - 254
Cited by:  Papers (16)
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This paper focuses on the problem of scheduling wafer lots on diffusion workstations in a semiconductor wafer fabrication facility. In a diffusion workstation, there are multiple identical machines, and each of them can process a (limited) number of wafer lots at a time. Wafer lots can be classified into several product families, and wafer lots that belong to the same product family can be process... View full abstract»

• ### Continuously Improving Methods for Increasing the Running Efficiency of Equipment in 300-mm Semiconductor Fabrication

Publication Year: 2010, Page(s):255 - 262
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Overall equipment efficiency (OEE) is widely adopted in semiconductor manufacturing to assess and enhance equipment productivity. The rate efficiency, which is a major component of OEE, is utilized to evaluate the achievement of actual production rate to the equipment's theoretical production rate. However, the rate efficiency is significantly influenced by factors beyond the equipment and, theref... View full abstract»

• ### Analysis of Interaction Structure Among Multiple Functional Process Variables for Process Control in Semiconductor Manufacturing

Publication Year: 2010, Page(s):263 - 272
Cited by:  Papers (3)
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Our previous work has shown that complex interaction patterns among functional process variables (FPVs) in semiconductor manufacturing processes can indicate process condition changes. We developed a nonlinear dynamics model to describe interactions among FPVs, which was further used to monitor process condition changes. However, the interaction structure among three or more FPVs has not been thor... View full abstract»

• ### Structural Feature-Based Fault-Detection Approach for the Recipes of Similar Products

Publication Year: 2010, Page(s):273 - 283
Cited by:  Papers (5)
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The sensor signals (i.e., data streams of process parameters) of semiconductor processes exhibit nonlinear, multimodal trajectories with some common structural features. In this paper, we propose a process fault-detection approach based on the structural features of the sensor signals, such as the geometric shape, length, and height. The approach aims at constructing a shared univariate model and ... View full abstract»

• ### A Wavelet-Based Approach in Detecting Visual Defects on Semiconductor Wafer Dies

Publication Year: 2010, Page(s):284 - 292
Cited by:  Papers (5)
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The objective of this paper is to implement a two-dimensional wavelet transform (2-D WT) approach for detecting visual defects such as particles, contamination, and scratches on semiconductor wafer dies. The gray image of 1/20 of a wafer die is initially processed by smooth and high-pass filters. Then, it is decomposed directly by 2-D WT at multiple scales and different wavelet bases. The intersca... View full abstract»

• ### 300-mm Production-Worthy Magnetically Enhanced Non-Bosch Through-Si-Via Etch for 3-D Logic Integration

Publication Year: 2010, Page(s):293 - 302
Cited by:  Papers (5)
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We report a process development route toward 300-mm production-worthy non-Bosch through-silicon-via (TSV) etch with critical dimensions between 1-5 ¿¿m and aspect ratios up to 20:1 for 3-D logic applications. The etch development was performed on an experimental alpha-tool: a magnetically enhanced capacitively coupled plasma etcher with a dipole ring magnet that aims to capture the strengths (anis... View full abstract»

• ### Investigation of Pattern Effects in Rapid Thermal Processing Technology: Modeling and Experimental Results

Publication Year: 2010, Page(s):303 - 310
Cited by:  Papers (5)
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During rapid thermal processing, nonuniformity of local radiative properties in the wafer front side is now obviously identified to results in thermal dispersion at die scale. This leads to changes in annealing temperature and thus variabilities of electrical behavior and device performances. However, these detrimental contributors remain a hard job to manage. Indeed, both optical and thermal phys... View full abstract»

• ### Spacer Gate Lithography for Reduced Variability Due to Line Edge Roughness

Publication Year: 2010, Page(s):311 - 315
Cited by:  Papers (9)
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The effect of gate line edge roughness (LER) on bulk-Si MOSFET performance is studied using 3-D device simulations. The benefit of using a spacer (sidewall transfer) gate lithography process to mitigate the effect of LER is assessed, with consideration of source/drain placement and spacer width variation. The simulation results indicate that spacer gate lithography can dramatically reduce LER-indu... View full abstract»

• ### Process Performance Prediction for Chemical Mechanical Planarization (CMP) by Integration of Nonlinear Bayesian Analysis and Statistical Modeling

Publication Year: 2010, Page(s):316 - 327
Cited by:  Papers (15)
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Chemical mechanical planarization (CMP) process has been widely used in the semiconductor manufacturing industry for realizing highly finished (Ra ~ 1 nm) and planar surfaces (WIWNU ~ 1%, thickness standard deviation (SD) ~ 3 nm) of in-process wafer polishing. The CMP process is rather complex with nonlinear and non-Gaussian process dynamics, which brings significant challenges for process monitor... View full abstract»

• ### The Growth of Thin Silicon Oxide and Silicon Nitride Films at Low Temperature (400 $^{circ}{hbox{C}}$ ) and High Growth Rates for Semiconductor Device Fabrication by an Advanced Low Electron Temperature Microwave-Excited High-Density Plasma System

Publication Year: 2010, Page(s):328 - 339
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An advanced approach for the growth of thin and ultra-thin oxide and nitride films at low temperatures (400?C) for the fabrication of future scaled-down semiconductor electron devices is presented. This technique presents an alternative to the existing conventional thermal techniques currently employed in the IC industry, which utilize high-temperatures (800?C-1000?C) for the growth of both SiO View full abstract»

• ### Alternating Reversed Scanning Sequence for Improved Within-Wafer Uniformity During Nonmelt Laser Annealing of Arsenic-Implanted Silicon

Publication Year: 2010, Page(s):340 - 343
Cited by:  Papers (1)
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Beyond the 45-nm technology node, nonmelt laser thermal annealing (LTA) is a potential candidate to replace the spike rapid thermal annealing (RTA) for the formation of ultrashallow and highly activated source/drain extension junctions. However, one major drawback of LTA is that it is ineffective in the removal of implantation-induced damage. As such, arsenic deactivation, as a result of cluster f... View full abstract»

• ### 2010 IEEE International Interconnect Technology Conference

Publication Year: 2010, Page(s): 344
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## Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
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University of Arizona
Tucson, AZ  85721

Publications Office Contact:
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