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Semiconductor Manufacturing, IEEE Transactions on

Issue 2 • Date May 2010

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  • Table of contents

    Publication Year: 2010 , Page(s): C1 - C4
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  • IEEE Transactions on Semiconductor Manufacturing publication information

    Publication Year: 2010 , Page(s): C2
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  • Introduction to the Special Section on Advanced Process Control

    Publication Year: 2010 , Page(s): 149 - 150
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  • Model Regularization for High-Mix Control

    Publication Year: 2010 , Page(s): 151 - 158
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (725 KB) |  | HTML iconHTML  

    Past solutions to the multicontext run-to-run control problem are examined, especially in how they attempt to resolve ill-posedness of the model that leads to a lack of observability. The specific models examined in this paper are assumed to contain a combination of terms, each partitioned by a different context. It is shown that none of the past approaches adequately addresses the observability issue. This lack of observability has been known to cause sporadic excursions in practice due to the phenomena of estimation error drift. In this paper, a regularization scheme is presented that is shown to address this issue. A novel aspect of the proposed approach is the use of model augmentation versus model reduction or forcing reference values. The resulting regularized models are amenable to a variety of recursive estimation schemes. Last, simulations and production data are used to validate the behavior of the proposed approach. View full abstract»

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  • Properties of EWMA Controllers With Gain Adaptation

    Publication Year: 2010 , Page(s): 159 - 167
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (922 KB) |  | HTML iconHTML  

    Exponentially weighted moving average (EWMA) controllers are the most commonly used run-to-run controllers in the semiconductor industry. Using a linear model, an EWMA controller can be implemented in two different ways: either process gain or process intercept can be updated using EWMA statistics at each run. The most commonly used EWMA controller formulation is to keep the process gain as its off-line estimate and update the intercept term at each run. We term this formulation as "EWMA controller with intercept adaptation (EWMA-I)", and its properties have been extensively studied and well understood. We term the other implementation, i.e., keeping the intercept term as its off-line estimate and updating the process gain at each run, as "EWMA with gain adaptation (EWMA-G)". Despite the fact that gain variation and adaptation is typical in the semiconductor industry, little research has been done to investigate the properties of an EWMA-G controller, such as its stability and sensitivity. In this work, the stability and sensitivity properties of an EWMA-G controller are investigated and compared with those of an EWMA-I controller. Both stationary and drifting processes are considered. In addition, the expressions of the process outputs are derived and the output variances for stochastic processes are evaluated. Simulation examples are given to illustrate these properties and the relevance of these properties to semiconductor process control is discussed. The analysis results will provide some useful guidance on the industrial applications of the EWMA controllers. View full abstract»

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  • Compensating for the Initialization and Sampling of EWMA Run-to-Run Controlled Processes

    Publication Year: 2010 , Page(s): 168 - 177
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (486 KB) |  | HTML iconHTML  

    The exponentially weighted moving average (EWMA) filter is commonly used for state estimation of run-to-run controllers in semiconductor manufacturing. It is widely known that, when at steady state, the EWMA filter provides the minimum mean square error (MSE) forecast for an integrated moving average (IMA) process. The forecast, however, is optimal if and only if every output of the IMA process is measured. If an EWMA controller is implemented utilizing sampled process data, then it is necessary to retune the controller to maintain optimal performance. Furthermore, in practice, the complex interacting selection criteria of advanced sampling applications often cause measurement frequency to be highly irregular. In this paper, a sampling compensation algorithm (SCA) is derived based on the minimum-norm IMA (MNIMA) forecast. The algorithm provides the minimum mean-square-error (MMSE) forecast of an IMA process for irregularly sampled processes and is robust to initialization. View full abstract»

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  • Optimization Solvers in Run-to-Run Control

    Publication Year: 2010 , Page(s): 178 - 184
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1618 KB) |  | HTML iconHTML  

    Semiconductor manufacturing processes with multiple settings or multiple targets, such as furnace applications or processes controlling uniformity, may not have a single algebraic solution, in which case optimization methods are required. While there are many optimization algorithms available, most are not guaranteed to find the global optimum, take longer than an analytic solution, and produce a less precise result. Despite this, in practice people use optimizers even when they are not needed. This paper explains when optimizers are needed and examines how the structure of the process model can be used to speed up the optimization process and ensure that the global optimum is found. View full abstract»

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  • Addressing Dynamic Process Changes in High Volume Plasma Etch Manufacturing by Using Multivariate Process Control

    Publication Year: 2010 , Page(s): 185 - 193
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1412 KB) |  | HTML iconHTML  

    Multivariate plasma etch modeling and control methodology are presented based on 65 and 45 nm gate production data utilizing wafer-to-wafer tool-level scatterometry. The selection of etch recipe variables for optimal control of wafer-to-wafer profile, within-wafer CD, and chamber-to-chamber CD is demonstrated and validated based on wafer-to-wafer, within wafer, and chamber matching experiments. View full abstract»

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  • Large-Scale Semiconductor Process Fault Detection Using a Fast Pattern Recognition-Based Method

    Publication Year: 2010 , Page(s): 194 - 200
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (859 KB) |  | HTML iconHTML  

    Fault detection and classification (FDC) has been recognized as an integral component of the advanced process control (APC) framework in the semiconductor industry, as it helps to improve overall equipment efficiency (OEE). However, some unique characteristics of semiconductor manufacturing processes have posed challenges for FDC applications, such as nonlinearity in most batch processes, and multimodal batch trajectories due to product mix. To explicitly account for these unique characteristics, a pattern recognition based fault detection method utilizing the k-nearest-neighbor rule (FD-kNN) was previously developed. In FD-kNN, historical data are used directly as the reference of normal process operation to determine whether a new measurement is a fault. Therefore, for processes with a large number of variables, it can be computation and storage intensive, and may be difficult for online process monitoring. To address this difficulty, we propose a fast pattern recognition based fault detection method, termed principal component-based kNN (PC-kNN), which takes advantages of both principal component analysis (PCA) for dimensionality reduction and FD-kNN for nonlinearity and multimode handling. Two simulation examples and an industrial example are used to demonstrate the performance of the proposed PC-kNN method in fault detection. View full abstract»

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  • Introducing a Unified PCA Algorithm for Model Size Reduction

    Publication Year: 2010 , Page(s): 201 - 209
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1007 KB) |  | HTML iconHTML  

    Principal component analysis (PCA) is a technique commonly used for fault detection and classification (FDC) in highly automated manufacturing. Because PCA model building and adaptation rely on eigenvalue decomposition of parameter covariance matrices, the computational effort scales cubically with the number of input variables. As PCA-based FDC applications monitor systems with more variables, or trace data with faster sampling rates, the size of the PCA problems can grow faster than the FDC system infrastructure will allow. This paper introduces an algorithm that greatly reduces the overall size of the PCA problem by breaking the analysis of a large number of variables into multiple analyses of smaller uncorrelated blocks of variables. Summary statistics from these subanalyses are then combined into results that are comparable to what is generated from the complete PCA of all variables together. View full abstract»

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  • Scheduling Back-End Operations in Semiconductor Manufacturing

    Publication Year: 2010 , Page(s): 210 - 220
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB) |  | HTML iconHTML  

    The importance of back-end operations in semiconductor manufacturing has been growing steadily in the face of higher customer expectations and stronger competition in the industry. In order to achieve low cycle times, high throughput and high utilization while improving due-date performance, more effective tools are needed to support machine setup and lot dispatching decisions. This paper presents a new model and solution methodology aimed at maximizing the weighted throughput of lots undergoing assembly and test, while ensuring that critical lots are given priority. The problem is formulated as a mixed-integer program and solved with a reactive greedy randomized adaptive search procedure (GRASP). In phase I of the GRASP, machine-tooling combinations are tentatively fixed and lot assignments are made iteratively to arrive at a feasible solution. This process is repeated many times. In phase II, a novel neighborhood search is performed on a subset of good solutions found in phase I. Using a linear programming-Monte Carlo simulation-based algorithm, new machine-tooling combinations are identified within the neighborhood of the solutions carried over, and improvements are sought by optimizing the corresponding lot assignments. The methodology was tested on data provided by a major semiconductor manufacturer. The results show that GRASP achieves high quality solutions comparable to those obtained with CPLEX in often half the time. View full abstract»

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  • Yield Management Enhanced Advanced Process Control System (YMeAPC)—Part I: Description and Case Study of Feedback for Optimized Multiprocess Control

    Publication Year: 2010 , Page(s): 221 - 235
    Cited by:  Papers (4)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2354 KB) |  | HTML iconHTML  

    In today's competitive semiconductor manufacturing environment, improving fab productivity and reducing cost requires that all systems work collaboratively towards production, quality and cost targets. Equipment engineering systems (EES), including advanced process control have risen to the top as key enablers for maximizing fab productivity, however these systems have been hindered as they focus on equipment and process, rather than fab-wide, metrics. Extending EES into the yield management space allows for leveraging yield prediction information as feedback into closing the loop around the fab to better achieve productivity goals. With this added capability of yield prediction, EES can: 1) predict yield excursions as well as excursion sources (leveraging virtual metrology technology), thereby avoiding costly post mortem yield recovery activities; 2) improve EES capabilities such as maintenance management and scheduling/dispatch; and 3) utilize yield prediction information as feedback to all levels of control in the fab, from individual processes up through factory-level controllers so that processes can be continuously tuned to meet yield and device performance targets without resorting to design changes to slower products. Case studies of application of this feedback information illustrate that benefits can be achieved from straight-forward applications, however these benefits can be expanded (especially) as more complex scheduling and control solutions are implemented. Realizing this type of yield-enhanced EES solution (YMeAPC) in a cost-effective manner requires fab-wide adherence to standards and best practices for component integration, event-based control system operation, and user interface management. View full abstract»

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  • Forward Echelon-Based Inventory Monitoring in a Semiconductor Supply Chain

    Publication Year: 2010 , Page(s): 236 - 245
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (636 KB) |  | HTML iconHTML  

    As the semiconductor industry faces fierce competition, it is essential for the semiconductor supply chain to integrate the front end and the back end to provide better service to customers. However, each member of the supply chain has different levels of power and pursues different goals which results in poor performance and difficulty monitoring it. In order to enhance service levels and to improve the performance of the whole supply chain, front-end members need to lead all of the other members to share information and to synchronize operations. Considering the characteristics of production and the substantial power of the front-end actors, this research develops a forward echelon-based inventory model for a semiconductor supply chain based on the concept of the echelon work in process (WIP) inventory and the CONWIP control method. We first construct the model that minimizes the echelon WIP upper limit under the target service levels. Next, we propose an algorithm for the model and validate the algorithm through a simulation study. Based on the results of the simulation study, we find that: 1) the algorithm derives the WIP upper limit effectively and 2) compared to the traditional stage-based inventory model, the forward echelon-based inventory model obtains a higher service level and a lower inventory level. View full abstract»

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  • Scheduling Wafer Lots on Diffusion Machines in a Semiconductor Wafer Fabrication Facility

    Publication Year: 2010 , Page(s): 246 - 254
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB) |  | HTML iconHTML  

    This paper focuses on the problem of scheduling wafer lots on diffusion workstations in a semiconductor wafer fabrication facility. In a diffusion workstation, there are multiple identical machines, and each of them can process a (limited) number of wafer lots at a time. Wafer lots can be classified into several product families, and wafer lots that belong to the same product family can be processed together as a batch. Processing times and setup times for wafer lots of the same product family are the same, but ready times of the wafer lots (at the diffusion workstation) may be different. We present several heuristic algorithms for the problem with the objective of minimizing total tardiness. For evaluation of performance of the suggested algorithms, a series of computational experiments is performed on randomly generated test problems. Results show that the suggested algorithms perform better than algorithms currently used in practice. View full abstract»

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  • Continuously Improving Methods for Increasing the Running Efficiency of Equipment in 300-mm Semiconductor Fabrication

    Publication Year: 2010 , Page(s): 255 - 262
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (481 KB) |  | HTML iconHTML  

    Overall equipment efficiency (OEE) is widely adopted in semiconductor manufacturing to assess and enhance equipment productivity. The rate efficiency, which is a major component of OEE, is utilized to evaluate the achievement of actual production rate to the equipment's theoretical production rate. However, the rate efficiency is significantly influenced by factors beyond the equipment and, therefore, is inadequate for deciding whether a low production rate is due to the equipment itself. Such an inaccurate evaluation of production rate of equipment usually results in productivity loss. Hence, this study develops a novel metric, called running efficiency (RUNE), to compare the actual and theoretical production rates of the equipment. The RUNE is not affected by the production environment and can be employed to determine sources of equipment's variation. Additionally, a RUNE management procedure is also proposed. The management procedure incorporates an automatic target-setting scheme to set the theoretical production time of every motion in equipment to obtain the RUNE value of equipment. An exponentially weighted moving average control chart is then utilized in the management procedure to monitor the RUNE value of equipment. A real case from a 300-mm fabrication in Taiwan is employed to demonstrate the effectiveness of the proposed method. View full abstract»

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  • Analysis of Interaction Structure Among Multiple Functional Process Variables for Process Control in Semiconductor Manufacturing

    Publication Year: 2010 , Page(s): 263 - 272
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1405 KB) |  | HTML iconHTML  

    Our previous work has shown that complex interaction patterns among functional process variables (FPVs) in semiconductor manufacturing processes can indicate process condition changes. We developed a nonlinear dynamics model to describe interactions among FPVs, which was further used to monitor process condition changes. However, the interaction structure among three or more FPVs has not been thoroughly investigated for the purpose of process control. In this work, we first extend our previously developed nonlinear dynamics model by considering the autocorrelation in each FPV. A generalized least square (GLS) method is applied to estimate the extended model. The interaction structure among FPVs is represented as a complex network in which the directionality and strength of interaction are discovered from the extended nonlinear dynamics model. To validate the proposed method, we first conduct simulation study using van del Pol oscillators. Then two sets of real experimental data from chemical mechanical planarization process are used to investigate the interaction structure change over a polishing cycle. The results show that the extracted patterns of interaction structure among FPVs aid to uncover the polishing mechanisms and provide more insights for condition monitoring and diagnosis. View full abstract»

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  • Structural Feature-Based Fault-Detection Approach for the Recipes of Similar Products

    Publication Year: 2010 , Page(s): 273 - 283
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (546 KB) |  | HTML iconHTML  

    The sensor signals (i.e., data streams of process parameters) of semiconductor processes exhibit nonlinear, multimodal trajectories with some common structural features. In this paper, we propose a process fault-detection approach based on the structural features of the sensor signals, such as the geometric shape, length, and height. The approach aims at constructing a shared univariate model and a multivariate model. The shared univariate model is set up for individual process parameters and clusters the process recipes of similar products. The result is a tree where the leaf nodes and intermediate nodes correspond to individual recipes and feature-based fault-detection criteria, respectively. The recipes with the same parent nodes share the criteria specified in the nodes. On the other hand, the multivariate model is constructed for a process recipe. It builds a Hotelling's T 2 that considers the correlations between the signal structures of the process parameters. We demonstrated that the test results of the two models using the data collected from a work-site etch process were encouraging. View full abstract»

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  • A Wavelet-Based Approach in Detecting Visual Defects on Semiconductor Wafer Dies

    Publication Year: 2010 , Page(s): 284 - 292
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3039 KB) |  | HTML iconHTML  

    The objective of this paper is to implement a two-dimensional wavelet transform (2-D WT) approach for detecting visual defects such as particles, contamination, and scratches on semiconductor wafer dies. The gray image of 1/20 of a wafer die is initially processed by smooth and high-pass filters. Then, it is decomposed directly by 2-D WT at multiple scales and different wavelet bases. The interscale ratio from the wavelet transform modulus sum (WTMS) across adjacent decomposition levels (scales) for suspicious pixels on a wafer die is calculated. Since irregular edges in a small domain preserve much more wavelet energy, an edge pixel potentially belongs to a visual defect if its interscale ratio is less than a predefined threshold. The proposed approach is template-free and is easy to implement, so it is suitable for more product varieties and small-batch production. Real wafer dies with synthetic defects are used as testing samples to evaluate the performance of proposed approach. Experimental results from a small amount of testing samples show that the proposed method is able to identify particle, contamination, and scratch defects without missed detection and false alarm by appropriate choice of wavelet bases, scale, and image resolution. The proposed inspection approach could be considered as a potentially precise and low detection error method for further large amounts of inspections in a real environment. View full abstract»

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  • 300-mm Production-Worthy Magnetically Enhanced Non-Bosch Through-Si-Via Etch for 3-D Logic Integration

    Publication Year: 2010 , Page(s): 293 - 302
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3132 KB) |  | HTML iconHTML  

    We report a process development route toward 300-mm production-worthy non-Bosch through-silicon-via (TSV) etch with critical dimensions between 1-5 ??m and aspect ratios up to 20:1 for 3-D logic applications. The etch development was performed on an experimental alpha-tool: a magnetically enhanced capacitively coupled plasma etcher with a dipole ring magnet that aims to capture the strengths (anisotropicity, profile uniformity) while eliminating the weaknesses (scalloping, undercut, residues) of a nominal Bosch process. Key factors contributing to the control of sidewall taper and roughness, etched TSV volume and depth, mask undercut, local bowing effects, and within wafer (WIW) center-to-edge depth and profile uniformity were evaluated. TSVs with nominal sizes of 5 ?? 25 ??m, 5 ?? 40 ??m and 1 ?? 20 ??m with less than 1% WIW nonuniformity, negligible silicon scalloping/mask undercut, and good profile anisotropicity were developed. Up to 3 ?? 20 ??m and 5 ?? 25 ??m void-free Cu-filled TSVs were demonstrated with both vertical TSVs and tapered TSVs. View full abstract»

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  • Investigation of Pattern Effects in Rapid Thermal Processing Technology: Modeling and Experimental Results

    Publication Year: 2010 , Page(s): 303 - 310
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1229 KB) |  | HTML iconHTML  

    During rapid thermal processing, nonuniformity of local radiative properties in the wafer front side is now obviously identified to results in thermal dispersion at die scale. This leads to changes in annealing temperature and thus variabilities of electrical behavior and device performances. However, these detrimental contributors remain a hard job to manage. Indeed, both optical and thermal physics are involved, a wide range of scales plays role, and many modeling challenges must be faced to understand and solve such issues. In this study, absorptivity and emissivity of various periodic patterned structures are investigated by optical modeling. It is clearly demonstrated that diffraction plays an important role when gate width dimension or space between gates become small. Then, the radiative properties can be mapped at die scale and hence a thermal simulation can be performed. Our intra-die simulated thermal gradient is in good agreement with experimental results. View full abstract»

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  • Spacer Gate Lithography for Reduced Variability Due to Line Edge Roughness

    Publication Year: 2010 , Page(s): 311 - 315
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1260 KB) |  | HTML iconHTML  

    The effect of gate line edge roughness (LER) on bulk-Si MOSFET performance is studied using 3-D device simulations. The benefit of using a spacer (sidewall transfer) gate lithography process to mitigate the effect of LER is assessed, with consideration of source/drain placement and spacer width variation. The simulation results indicate that spacer gate lithography can dramatically reduce LER-induced variation in transistor performance and that variability can be well suppressed with gate-length scaling even if LER does not scale. View full abstract»

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  • Process Performance Prediction for Chemical Mechanical Planarization (CMP) by Integration of Nonlinear Bayesian Analysis and Statistical Modeling

    Publication Year: 2010 , Page(s): 316 - 327
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1213 KB) |  | HTML iconHTML  

    Chemical mechanical planarization (CMP) process has been widely used in the semiconductor manufacturing industry for realizing highly finished (Ra ~ 1 nm) and planar surfaces (WIWNU ~ 1%, thickness standard deviation (SD) ~ 3 nm) of in-process wafer polishing. The CMP process is rather complex with nonlinear and non-Gaussian process dynamics, which brings significant challenges for process monitoring and control. As an attempt to address this issue, a method is presented in this paper that integrates nonlinear Bayesian analysis and statistical modeling to estimate and predict process state variables, and therewith to predict the performance measures, such as material removal rate (MRR), surface finish, surface defects, etc. As an example of performance measure, MRR is chosen to demonstrate the performance prediction. A sequential Monte Carlo (SMC) method, namely, particle filtering (PF) method is utilized for nonlinear Bayesian analysis to predict the CMP process-state and for tackling the process nonlinearity. Vibration signals from both wired and wireless vibration sensors are adopted in the experimental study conducted using the CMP apparatus. The process states captured by the sensor signals are related to MRR using design of experiments and statistical regression analysis. A case study was conducted using actual CMP processing data by comparing the PF method with other widely used prediction approaches. This comparison demonstrates the effectiveness of the proposed approach, especially for nonlinear dynamic processes. View full abstract»

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  • The Growth of Thin Silicon Oxide and Silicon Nitride Films at Low Temperature (400 ^{\circ}{\hbox {C}} ) and High Growth Rates for Semiconductor Device Fabrication by an Advanced Low Electron Temperature Microwave-Excited High-Density Plasma System

    Publication Year: 2010 , Page(s): 328 - 339
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1551 KB) |  | HTML iconHTML  

    An advanced approach for the growth of thin and ultra-thin oxide and nitride films at low temperatures (400?C) for the fabrication of future scaled-down semiconductor electron devices is presented. This technique presents an alternative to the existing conventional thermal techniques currently employed in the IC industry, which utilize high-temperatures (800?C-1000?C) for the growth of both SiO2 and Si3N4 films. An alternative is needed since the high temperature range given above limits further down-scaling possibilities of semiconductor electronic devices. In this paper, the structure, operational principles, and performance of a microwave-excited high-density (> 1012 cm-3) plasma system, which utilizes low bombardment inert gas ion energies (<7 eV), low plasma potential (<10 V), and low electron temperature (<1 eV), is described, which yields high-integrity SiO2 and Si3N4 films grown at 400?C. The films grown by this technique were previously shown by us to demonstrate comparable or superior performance with respect to SiO2 films grown by the conventional thermal method at much higher temperatures (1000?C). The specific issue which this paper addresses is the problem of the growth rate of these films, which are grown at the above reduced temperature. This issue is important because it affects the compatibility of this fabrication approach with the need to obtain a high throughput in industrial electronic device processing. The results clearly demonstrate that both the SiO2 and Si3N4 films grown at these low temperatures (400?C) exhibited comparable growth rates to those of films thermally grown by conventional techniques at elevated temperatures (800?C-1000?C). Data is presented of Silicon Oxide (SiO2) films grown with various inert gases (He, Ar, Kr, Xe), mixed with O2. Silicon Nitride (Si3- - N4) films were grown by using Ar/N2, Ar/N2/H2, and Ar/NH3 gas mixtures. Both film types were grown in a vacuum chamber using different partial and total pressures of the above gases. Plasma excitation of these gases was achieved by irradiating them with microwave frequencies of 2.45 or 8.3 GHz. MOS transistors were fabricated using gate oxide grown by the above plasma system, in order to demonstrate the system's compatibility with electronic device fabrication. View full abstract»

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  • Alternating Reversed Scanning Sequence for Improved Within-Wafer Uniformity During Nonmelt Laser Annealing of Arsenic-Implanted Silicon

    Publication Year: 2010 , Page(s): 340 - 343
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (390 KB) |  | HTML iconHTML  

    Beyond the 45-nm technology node, nonmelt laser thermal annealing (LTA) is a potential candidate to replace the spike rapid thermal annealing (RTA) for the formation of ultrashallow and highly activated source/drain extension junctions. However, one major drawback of LTA is that it is ineffective in the removal of implantation-induced damage. As such, arsenic deactivation, as a result of cluster formation due to the release of excess interstitials from the end-of-range (EOR) region, is observed when a post-LTA thermal budget is applied. Since conventional LTA comprises localized heating using a laser beam scanning the wafer front-side in a nonalternating sequence, different portions of the wafer will experience varying post-LTA thermal budget from the hotplate, depending on when the laser beam scans through it. Because dopant deactivation increases as the post-LTA thermal budget increases, severe degradation of the within-wafer uniformity is observed. To address this problem, a multiple-pulse, alternating reversed laser scanning technique is implemented to average out the differences in post-LTA thermal budget across the wafer between each pulse. Using such a scheme, the variations in subsequent dopant deactivation across the wafer is reduced and significant uniformity improvement of up to 50% is observed. View full abstract»

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  • 2010 IEEE International Interconnect Technology Conference

    Publication Year: 2010 , Page(s): 344
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    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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Anthony Muscat
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