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IEE Proceedings E - Computers and Digital Techniques

Issue 2 • Mar 1993

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Displaying Results 1 - 10 of 10
  • Colour quantisation for colour texture analysis

    Publication Year: 1993, Page(s):109 - 114
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (552 KB)

    The problem of describing texture colours in a concise way is analysed. This problem is formulated as a colour quantisation problem, where the texture image is quantised using the smallest number k of representative colours given some criteria. These colours are the texture characteristic colours, and an algorithm is proposed to obtain them. It is shown that a network of simple processing elements... View full abstract»

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  • Structural technique for fault-masking in asynchronous interfaces

    Publication Year: 1993, Page(s):81 - 91
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (892 KB)

    Asynchronous VLSI circuits have been proven to be more tolerant to persistent defects, such as stuck-at faults, than their clocked counterparts. However, such circuits are directly reactive to input stimuli and so they can be more vulnerable to transient faults at their inputs. The ability to tolerate such faults is most crucial for interface circuits, or transducers, which are the information ker... View full abstract»

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  • Reed-Muller universal logic module networks

    Publication Year: 1993, Page(s):105 - 108
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (220 KB)

    Describes Reed-Muller universal logic modules (RM-ULMs) and their use for the implementation of logic functions given in Reed-Muller (RM) form. A programmed algorithm is presented for the synthesis and optimisation of RM-ULM networks. The level-by-level minimisation procedure is based on the selection of control variables at different levels with the aim of maximising the number of discontinued br... View full abstract»

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  • Processor arrays for two-dimensional discrete Fourier transform

    Publication Year: 1993, Page(s):101 - 104
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (232 KB)

    Two new processor arrays for the 2D discrete Fourier transform are proposed. Both structural schemes are oriented towards VLSI technology. They can be used in the construction of high-throughput processors for multidimensional and fast Fourier transforms as well as triple matrix multiplication. The first structural scheme consists of two successively connected one-dimensional arrays of processor e... View full abstract»

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  • Faster line detection algorithms on enhanced mesh connected arrays

    Publication Year: 1993, Page(s):95 - 100
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (444 KB)

    The problem of detecting lines in an image with N edge pixels on mesh connected computers with N processors is considered, and four new and efficient algorithms which detect lines by performing a Hough transform are presented. The first algorithm runs in O(N12/+n) time on a 2D (2 dimensional) mesh, where n is the number of theta values considered. The second algorithm runs in O((N/n)... View full abstract»

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  • Study of the behaviour of Hubnet

    Publication Year: 1993, Page(s):134 - 144
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (704 KB)

    The behaviour of Hubnet is studied and analysed. A simulation model is developed from which the effect of the retry time on the performance of Hubnet is studied. It is shown that there is an inherent dependency between the packet length and the retry time. According to this dependency, retry time-values which are factors of the packet length exhibit superior performance in terms of reduced average... View full abstract»

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  • Mapping single and multiple multilevel structures onto the hypercube

    Publication Year: 1993, Page(s):115 - 118
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (256 KB)

    Introduces algorithms that map single and multiple multilevel structures onto the hypercube. For the case of the pyramid, which is a special multilevel structure, it is shown that a new algorithm is a compromise among existing algorithms with regard to cost and performance. Comparative analysis of the algorithms is carried out using analytical techniques and simulation results. View full abstract»

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  • Efficient multiplication algorithm over the finite fields GF(qm) where q=3, 5

    Publication Year: 1993, Page(s):92 - 94
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (196 KB)

    Galois field multiplication is central to coding theory. In many applications of finite fields, there is need for a multiplication algorithm which can be realised easily on VLSI chips. In the paper, what is called the Babylonian multiplication algorithm for using tables of squares is applied to the Galois fields GF(qm). It is shown that this multiplication method for certain Galois fiel... View full abstract»

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  • Event-driven logic (EDL) approach to digital systems representation and related design processes

    Publication Year: 1993, Page(s):119 - 126
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (448 KB)

    There is a well established and growing need for fast digital processors and fast digital systems generally in many areas of application. In the design of sequential logic in particular, the problems of clock skew and the fact that the clock period is essentially determined by the speed of the slowest parts of the system are significant limiting factors. An alternative way of approaching the repre... View full abstract»

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  • Link augmented binary (LAB)-tree architecture

    Publication Year: 1993, Page(s):127 - 133
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (468 KB)

    A new augmented binary-tree multiprocessor architecture, called LAB-tree, is proposed. It consists of an n-level full/binary tree augmented with (2n-2) redundant links. The short and regular redundant links improve several properties of the full/binary tree, such as increased tolerance, reduced traffic congestion and efficient routing of messages. It is shown that there exist at least t... View full abstract»

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