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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 5 • Date May 2010

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Table of contents

IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Unified Logical Effort—A Method for Delay Evaluation and Minimization in Logic Paths With $RC$ Interconnect

Understanding the Effect of Process Variations on the Delay of Static and Domino Logic

A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits

A Mesh-Structured Scalable IPsec Processor

A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization

Resource Based Optimization for Simultaneous Shield and Repeater Insertion

A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors

A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies

Gate-Level Redundancy: A New Design-for-Reliability Paradigm for Nanotechnologies

Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy

Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation

An Efficient 4-D 8PSK TCM Decoder Architecture

Implementation of a Self-Motivated Arbitration Scheme for the Multilayer AHB Busmatrix

Interframe Bus Encoding Technique and Architecture for MPEG-4 AVC/H.264 Video Compression

Power Estimation of Embedded Multiplier Blocks in FPGAs

A Multibank Memory-Based VLSI Architecture of DVB Symbol Deinterleaver

VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory

Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of ${\rm GF}(2^{m})$

Low-Power Multimedia System Design by Aggressive Voltage Scaling

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