# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 36

Publication Year: 2010, Page(s):C1 - C4
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2010, Page(s): C2
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• ### Changes to the Editorial Board

Publication Year: 2010, Page(s): 965
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• ### Ultrashallow TiC Source/Drain Contacts in Diamond MOSFETs Formed by Hydrogenation-Last Approach

Publication Year: 2010, Page(s):966 - 972
Cited by:  Papers (11)  |  Patents (1)
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Applying the hydrogen (H) radical exposure at the last step of MOSFET fabrication process, an oxygen (O)-terminated channel was converted to a H-terminated one to obtain subsurface hole accumulation for field-effect transistor operation. Low-resistive titanium carbide (TiC) source/drain and alumina gate oxide were resistant to the hydrogenation process. The shallow TiC side contacts (~ 3 nm in dep... View full abstract»

• ### Silane and Ammonia Surface Passivation Technology for High-Mobility $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs

Publication Year: 2010, Page(s):973 - 979
Cited by:  Papers (52)
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We report the integration of silane and ammonia (SiH4 + NH3) surface passivation technology to realize high-quality gate stack on a high-mobility In0.53Ga0.47As compound semiconductor. Vacuum anneal at 520°C desorbs the native oxide while preserving the surface morphology and material composition of In0.53Ga0.47As. By incorpora... View full abstract»

• ### AlN Passivation Over AlGaN/GaN HFETs for Surface Heat Spreading

Publication Year: 2010, Page(s):980 - 985
Cited by:  Papers (27)  |  Patents (1)
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Reduction of thermal resistance in AlGaN/GaN heterojunction field-effect transistors (HFETs) is critical for further increase in their output power to be handled in these promising material systems. In this paper, we present a new technique to reduce it using polycrystalline AlN passivation deposited by dc sputtering as a surface heat spreader over AlGaN/GaN HFETs. The AlN is deposited by dc sputt... View full abstract»

• ### Analysis of Contact Effects in Inverted-Staggered Organic Thin-Film Transistors Based on Anisotropic Conduction

Publication Year: 2010, Page(s):986 - 994
Cited by:  Papers (12)
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In this paper, we propose an analytic model for inverted-staggered organic thin-film transistors, and we use the proposed model to investigate the dependence of contact effect on the voltage bias, the film thickness of the organic semiconductor, and the channel length. In our model, the variable-range-hopping transport is adopted for the conduction in the horizontal direction to the semiconductor-... View full abstract»

• ### Large-Area Flexible Ultrasonic Imaging System With an Organic Transistor Active Matrix

Publication Year: 2010, Page(s):995 - 1002
Cited by:  Papers (41)
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We have successfully fabricated a large-area flexible ultrasonic imaging system by integrating a polymeric ultrasonic-transducer array sheet with an active matrix of organic field-effect transistors. The ultrasonic sheet comprises 8 x 8 ultrasonic sensing cells with an effective size of 25 Ã 25 cm2. The organic transistors exhibit mobility of 0.1 and 0.5 cm2/V Â·s at the low... View full abstract»

• ### Bias-Stress Effect in Pentacene Organic Thin-Film Transistors

Publication Year: 2010, Page(s):1003 - 1008
Cited by:  Papers (41)
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The effects of bias stress in integrated pentacene organic transistors are studied and modeled for different stress conditions. It is found that the effects of bias stress can be expressed in terms of the shift in applied gate voltage Â¿V for a given current. An empirical equation describing Â¿V in terms of different gate and drain bias stress measurements and stress times is presented and verifie... View full abstract»

• ### Effect of Metallic Composition on Electrical Properties of Solution-Processed Indium-Gallium-Zinc-Oxide Thin-Film Transistors

Publication Year: 2010, Page(s):1009 - 1014
Cited by:  Papers (40)
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We report the combinatorial study on surface morphology and electrical properties of solution-processed amorphous indium-gallium-zinc-oxide (a- IGZO) thin-film transistors (TFTs). The sol-gel-processed a-IGZO thin films typically have shown an amorphous structure and critical dependence of mobility, carrier concentration, and surface roughness on the In, Ga, and ... View full abstract»

• ### An Empirical Defect-Related Photo Leakage Current Model for LTPS TFTs Based on the Unit Lux Current

Publication Year: 2010, Page(s):1015 - 1022
Cited by:  Papers (2)
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In this paper, the photosensitive effect of n-type low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) after dc stress is analyzed. It is found that the illumination behaviors for poly-Si TFTs are dependent on the defect types created by different stress conditions of hot-carrier and self-heating effects. For a given stress-induced device degradation, the anomalous illumina... View full abstract»

• ### True Energy-Performance Analysis of the MTJ-Based Logic-in-Memory Architecture (1-Bit Full Adder)

Publication Year: 2010, Page(s):1023 - 1028
Cited by:  Papers (30)
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The use of spin-transfer torque (STT) devices for memory design has been a subject of research since the discovery of the STT on MgO-based magnetic tunnel junctions (MTJs). Recently, MTJ-based computing architectures such as logic-in-memory have been proposed and claim superior energy-delay performance over static CMOS. In this paper, we conduct exhaustive energy-performance analysis of an STT-MTJ... View full abstract»

• ### Simple Analytical Model of the Thermal Resistance of Resistors in Integrated Circuits

Publication Year: 2010, Page(s):1029 - 1036
Cited by:  Papers (3)
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The value of resistors generally changes with electrical current. For precision analog circuit layout, it is important to predict those resistance variations. For that purpose, we derive for the first time a simple analytic 3-D model to describe thermal resistance and self-heating, which we show as the dominant contribution to resistor nonlinearity for a wide range of resistors. The model shows go... View full abstract»

• ### Uniaxial Stress Engineering for High-Performance Ge NMOSFETs

Publication Year: 2010, Page(s):1037 - 1046
Cited by:  Papers (19)
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Ge channel is one of the promising performance boosters for replacing Si channel in future complementary metal-oxide-semiconductor technology. The uniaxial stress technology can further enhance the performance of Ge MOSFETs. In this paper, the uniaxial stress effect on Ge NMOSFETs was experimentally and theoretically investigated. The gate dielectric in the Ge NMOSFETs was fabricated by using the ... View full abstract»

• ### Threshold-Switching Delay Controlled by $hbox{1}/f$ Current Fluctuations in Phase-Change Memory Devices

Publication Year: 2010, Page(s):1047 - 1054
Cited by:  Papers (18)
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Threshold switching, i.e., the electrical transition from high to low resistivity in amorphous semiconductors, plays a major role in the program/erase processes of phase-change memory (PCM) devices. Understanding and designing materials and cell structures for optimum memory performance require that accurate models for threshold switching be developed, in both the steady-state and the transient re... View full abstract»

• ### A Simulation Study of the Punch-Through-Assisted Hot Hole Injection Mechanism for Nonvolatile Memory Cells

Publication Year: 2010, Page(s):1055 - 1062
Cited by:  Papers (3)
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In this paper, we investigate the operating principle and the injection efficiency of the punch-through-assisted hot hole injection mechanism for programming nonvolatile memory cells by means of full-band Monte Carlo transport simulations of realistic device structures. The effects of terminal bias and cell scaling on the injection efficiency and the uniformity of charge injection along the channe... View full abstract»

• ### RF Characterization of Schottky Diodes in 65-nm CMOS

Publication Year: 2010, Page(s):1063 - 1068
Cited by:  Papers (15)
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Schottky diodes in 65-nm CMOS have been designed, measured up to 67 GHz, and modeled in the reverse-bias voltage range. An array of 8 ¿¿ 8 minimum-sized parallel diode junctions is compared with a single-junction diode and to linear arrays of 3, 12, and 64 elements of the same total area. An iterative analysis method and a more detailed equivalent circuit than that used in previous work are develo... View full abstract»

• ### A Physical Model for Fringe Capacitance in Double-Gate MOSFETs With Non-Abrupt Source/Drain Junctions and Gate Underlap

Publication Year: 2010, Page(s):1069 - 1075
Cited by:  Papers (13)  |  Patents (1)
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For the first time, the inner and outer components of the parasitic gate-source/drain (G-S/D) fringe capacitance in nanoscale double-gate (DG) metal-oxide-semiconductor field-effect transistors, with nonabrupt S/D-body junctions that define effective G-S/D underlap, are physically modeled in terms of the device structure. The model relates the fringe capacitance to the device short-channel effects... View full abstract»

• ### Compact Layout of On-Chip Transformer

Publication Year: 2010, Page(s):1076 - 1083
Cited by:  Papers (6)
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This study develops a compact layout for an on-chip transformer with both wide range of turn ratios and a high coupling coefficient in a small chip area. Analytical formulas are applied to calculate the self-inductances in the design stage. Therefore, six devices with various turn ratios are designed to verify the proposed layout. All devices are fabricated using foundry 130 nm complementary metal... View full abstract»

• ### Dopant-Segregated Schottky Junction Tuning With Fluorine Pre-Silicidation Ion Implant

Publication Year: 2010, Page(s):1084 - 1092
Cited by:  Papers (11)
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Dopant-segregated Schottky (DSS) junctions are formed by implant-to-silicide (ITS) processing with NiSi. It is shown that a fluorine pre-silicidation ion implant (F-PSII) can be used to reduce the depth of the doped Si region. This provides a new means for engineering the source/drain extension regions in DSS source/drain MOSFETs for performance optimization. It is also shown that there are two di... View full abstract»

• ### Parameter Extraction of Short-Channel a-Si:H TFT Including Self-Heating Effect and Drain Current Nonsaturation

Publication Year: 2010, Page(s):1093 - 1101
Cited by:  Papers (8)
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We present an extraction procedure of the above-threshold parameters of a modified level-15 model of hydrogenated amorphous-silicon thin-film transistors (a-Si:H TFTs). This procedure is useful for model parameter extraction for short-channel devices, including the self-heating effect (SHE) and the nonsaturating drain current effect via the channel length modulation (CLM). The drain current formul... View full abstract»

• ### Simulation of Quantum Current Oscillations in Trigate SOI MOSFETs

Publication Year: 2010, Page(s):1102 - 1109
Cited by:  Papers (10)
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In this paper, we simulate quantum transport in trigate silicon-on-insulator (SOI) nanowire field-effect transistors using 3-D numerical simulations. The formation of 1-D subbands in SOI nanowire, which results in the oscillation of the current and transconductance characteristic at low temperatures, has been studied in detail. These oscillations correspond to the filling of energy subbands by ele... View full abstract»

• ### Physics-Based Analysis and Simulation of $hbox{1}/f$ Noise in MOSFETs Under Large-Signal Operation

Publication Year: 2010, Page(s):1110 - 1118
Cited by:  Papers (6)
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This paper presents a study on 1/f noise in MOSFETs under large-signal (LS) operation, which is important in CMOS analog and RF integrated circuits. The flicker noise is modeled with noise sources as a perturbation in the semiconductor equations employing McWhorter's oxide-trapping model and Hooge's empirical 1/f noise model. Numerical results are shown for 1/f noise in the MOSFET in both small-si... View full abstract»

• ### Reduction of RTS Noise in Small-Area MOSFETs Under Switched Bias Conditions and Forward Substrate Bias

Publication Year: 2010, Page(s):1119 - 1128
Cited by:  Papers (15)  |  Patents (4)
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Low-frequency noise in small-area MOSFETs is dominated by random telegraph signal noise associated to the capture and emission of charge carriers by a single trap located in the gate dielectric. RTS noise degrades the performance of analog, digital, and memory circuits. In this paper, we present measurements and simulations of RTS noise in small-area MOSFETs under constant bias and switched gate b... View full abstract»

• ### Universal Tunnel Mass and Charge Trapping in $[( hbox{SiO}_{2})_{1-x} (hbox{Si}_{3}hbox{N}_{4})_{x}]_{1-y}hbox{Si}_{y}$ Film

Publication Year: 2010, Page(s):1129 - 1136
Cited by:  Papers (6)
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Although the tunnel mass is indispensable to predict the gate leakage current of electron devices, it has been regarded as an adjustable parameter to fit the calculated leakage current with the measured ones. This appears useful because it enables calculation of the tunnel current while ignoring some details in advanced device modeling, even though it has veiled the intuitive nature of the modelin... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy